: make verilate error (EAN6/ESP5 ORPSoC with Verilator)

[vinut]

Hii,
I am  facing  problem with make verilate..
I am getting an error like this.
Pleae reply..
cd sim/src && ln -s ../../local/sw/dhry/dhry-icdc-O2.hex flash.in
cd verilator-model && time -p make
make[1]: Entering directory `/home/vinitha/simulations/Or1200_1/orpsoc-models-1.0/verilator-model'
Makefile:121: OrpsocAccess.d: No such file or directory
Makefile:121: TraceSC.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ALLcls.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ALLsup.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ver.d: No such file or directory
/bin/sh: cf-base-line.scr: No such file or directory
make[1]: *** [Vorpsoc_fpga_top.mk] Error 1
make[1]: Leaving directory `/home/vinitha/simulations/Or1200_1/orpsoc-models-1.0/verilator-model'
real 0.00
user 0.00
sys 0.00
make: *** [model] Error 2


Regards
Vinitha

[vinut]

Hii,
    I am facing problem with make verilate .The error i am getting is ,
 make verilate COMMAND_FILE=cf-baseline-5.scr VFLAGS="-Wno-lint -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001"
Makefile:85: warning: overriding commands for target `has'
Makefile:80: warning: ignoring old commands for target `has'
Makefile:85: warning: overriding commands for target `not'
Makefile:80: warning: ignoring old commands for target `not'
Makefile:85: warning: overriding commands for target `been'
Makefile:80: warning: ignoring old commands for target `been'
Makefile:93: warning: overriding commands for target `"VTARGET'
Makefile:85: warning: ignoring old commands for target `"VTARGET'
Makefile:93: warning: overriding commands for target `has'
Makefile:85: warning: ignoring old commands for target `has'
Makefile:93: warning: overriding commands for target `not'
Makefile:85: warning: ignoring old commands for target `not'
Makefile:93: warning: overriding commands for target `been'
Makefile:85: warning: ignoring old commands for target `been'
Makefile:121: OrpsocAccess.d: No such file or directory
Makefile:122: "VTARGET: No such file or directory
Makefile:122: has: No such file or directory
Makefile:122: not: No such file or directory
Makefile:122: been: No such file or directory
Makefile:122: set"__ALLcls.d: No such file or directory
Makefile:122: "VTARGET: No such file or directory
Makefile:122: has: No such file or directory
Makefile:122: not: No such file or directory
Makefile:122: been: No such file or directory
Makefile:122: set"__ALLsup.d: No such file or directory
Makefile:122: "VTARGET: No such file or directory
Makefile:122: has: No such file or directory
Makefile:122: not: No such file or directory
Makefile:122: been: No such file or directory
Makefile:122: set"__ver.d: No such file or directory
make: Circular "VTARGET <- "VTARGET dependency dropped.
make: Circular has <- "VTARGET dependency dropped.
make: Circular has <- has dependency dropped.
make: Circular not <- "VTARGET dependency dropped.
make: Circular not <- has dependency dropped.
make: Circular not <- not dependency dropped.
make: Circular been <- "VTARGET dependency dropped.
make: Circular been <- has dependency dropped.
make: Circular been <- not dependency dropped.
make: Circular been <- been dependency dropped.
make -f "VTARGET has not been set".mk "VTARGET has not been set"__ALL.a
make[1]: Entering directory `/home/vinitha/test/embecosm-esp5-or1k-verilator-1.0/verilator-model'
make[1]: VTARGET has not been set.mk: No such file or directory
make[1]: *** No rule to make target `VTARGET has not been set.mk'.  Stop.
make[1]: Leaving directory `/home/vinitha/test/embecosm-esp5-or1k-verilator-1.0/verilator-model'
make: *** [set"__ALL.a] Error 2
[vinitha@gs15] >
please help...
It seems my systemC and verilator installation is ok.Because verilator converts sample verilog code to systemC module.
Regards
Vinitha