AN2789 - MPC5500 Configuration and Initialization

I have been experimenting with Freescales, MPC5500 initialization code
and wonder if someone could clarify a few things for me. Running down
the list of configuration functions:

cfg_CACHE - If I understand, the cache is not active out of reset, so
this simply enables it. (1) Why wouldn't you want to do this? (2) If
you know the particular part has cache, is there a need to check
L1CFG0?

cfg_FMPLL - The Reference refers to setting the clock with your final
values with RFD+1, then reducing RFD after lock. (1) Why would you
want to set the clock to a series of rates, waiting for locks, such as
the 132MHz example? (2) What is the significance of inhibiting the
cache?

cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably
bad--more than just loosing ECC, it may flip bits incorrectly on read?

cfg_FLASH - What has changed at this point to allow less internal
flash wait states?

cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any
reason to worry about this?

Thanks in advance.
Steve