ATLAS 3.8.3 released

[Clint Whaley]

I have released 3.8.3.  This is, of course, mainly a bugfix release.
However, I have also backported some assembly kernels from the 3.9 series
for the Core2 and AMD64K10h architectures.  We have architectural defaults
for these systems, as well as the new Corei7 (64 bit only).  For Core2-based
systems, the speedup is substantial (K10h speedup is modest).

You should also be aware of one error, *which has not been fixed in 3.8.3*
   http://math-atlas.sourceforge.net/errata.html#scal0

Cheers,
Clint

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** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
**************************************************************************

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[Michael Abshoff-3]

On Wed, Feb 18, 2009 at 2:07 PM, Clint Whaley <whaley@...> wrote:

Hi Clint,

> I have released 3.8.3.  This is, of course, mainly a bugfix release.
> However, I have also backported some assembly kernels from the 3.9 series
> for the Core2 and AMD64K10h architectures.  We have architectural defaults
> for these systems, as well as the new Corei7 (64 bit only).  For Core2-based
> systems, the speedup is substantial (K10h speedup is modest).

Excellent, I really like the new Core i7 kernel and the improved Core2
performance in the stable series.

> You should also be aware of one error, *which has not been fixed in 3.8.3*
>   http://math-atlas.sourceforge.net/errata.html#scal0
>
> Cheers,
> Clint

While applying my patches I was glad to see that many fixes from 3.9.x
that I used in Sage's 3.8.2 were backported. But I noticed that in
archinfo_x86.c you did not add the "case 6" for the Pentium IV models
while the missing CPU IDs for the various other missing CPUs you had
listed at the errata page were added. The "case 6" are Pentium Ds IIRC
or maybe some P IV base Extreme Edition Intel CPU IIRC.

In 3.8.3 you have:

   case Pentium4:
      switch(model)
      {
      case 0:
      case 1:
      case 2:
         iret = IntP4;
         break;
      case 3:
      case 4:
         iret = IntP4E;
         break;
      default:
         iret = MACHOther;
      }

I used to apply the following patch:

@@ -310,7 +311,7 @@
          iret = IntP4;
          break;
       case 3:
-      case 4:
+      case 4: ; case 6:
          iret = IntP4E;
          break;
       default:

Let me know if you want this in SF's bug tracker.

Keep up the good work :)

Cheers,

Michael

> **************************************************************************
> ** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
> **************************************************************************
>
> ------------------------------------------------------------------------------
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[Clint Whaley]

Michael,

>While applying my patches I was glad to see that many fixes from 3.9.x
>that I used in Sage's 3.8.2 were backported. But I noticed that in
>archinfo_x86.c you did not add the "case 6" for the Pentium IV models
>while the missing CPU IDs for the various other missing CPUs you had
>listed at the errata page were added. The "case 6" are Pentium Ds IIRC
>or maybe some P IV base Extreme Edition Intel CPU IIRC.

OK, the reason this didn't get backported is that it is not in the 3.9.x
series either.  This means that I was unaware of it.  Now, in perfect
world, that would mean nobody had informed me that configure needed to
be amended, but I'm guessing you are going to tell me that I lost some
mail or forgot about a bug/support tracker item somewhere?

Thanks
Clint

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**************************************************************************

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[Michael Abshoff-3]

On Fri, Feb 20, 2009 at 1:10 PM, Clint Whaley <whaley@...> wrote:
> Michael,

Hi Clint,

>>While applying my patches I was glad to see that many fixes from 3.9.x
>>that I used in Sage's 3.8.2 were backported. But I noticed that in
>>archinfo_x86.c you did not add the "case 6" for the Pentium IV models
>>while the missing CPU IDs for the various other missing CPUs you had
>>listed at the errata page were added. The "case 6" are Pentium Ds IIRC
>>or maybe some P IV base Extreme Edition Intel CPU IIRC.
>
> OK, the reason this didn't get backported is that it is not in the 3.9.x
> series either.  This means that I was unaware of it.  Now, in perfect
> world, that would mean nobody had informed me that configure needed to
> be amended, but I'm guessing you are going to tell me that I lost some
> mail or forgot about a bug/support tracker item somewhere?

Well, it was on the errata page according to
http://trac.sagemath.org/sage_trac/ticket/3787 at some point:

Note the the remark I added "And I figure it is better to quote the
solution since the errata page tends to get updated quite a bit:"
followed by

[quote]
To fix this, simply comment out lines 95 and 99 of ATLAS/CONFIG/src/backend
/archinfo_x86.c. So, change line 95 from:

   if (*family == 0xf || *family == 0) /* extended family is added in */

to:

/* if (*family == 0xf || *family == 0)*/ /* extended family is added in */

and change line 99 from

   if (*model == 0xf)                  /* extended model is concatenated */

to:

/* if (*model == 0xf)*/                /* extended model is concatenated */

Essentially, all the Core2-based systems are treated the same by ATLAS. So,
to get to use the architectural defaults on Core2-based XEONs, change line
297 from:

      case 15:

to:

      case 15: ; case 23:

Finally, to enable better P4E identification, change line 313 from:

      case 4:

to:

      case 4: ; case 6:
[end quote]

So unless your evil twin edited the page this got somehow lost.

> Thanks
> Clint

Anyway, I am having two things I am currently interested in:

 * Itanium CPU identification. This CPU:

processor  : 3
vendor     : GenuineIntel
arch       : IA-64
family     : Itanium 2
model      : 0
revision   : 7
archrev    : 0
features   : branchlong, 16-byte atomic ops
cpu number : 0
cpu regs   : 4
cpu MHz    : 1594.000733
itc MHz    : 399.181840
BogoMIPS   : 3186.68
siblings   : 2
physical id: 3
core id    : 1
thread id  : 0

Running either RHEL 5 or SLES 10 is misidentified as a Itanium with
standard ATLAS 3.8.3. I haven't poked around in the detection routines
yet, but ATLAS might be missing a couple CPUids. For now I just force
every Itanium to be an Itanium 2. Give the number of Itaniums in the
wild I haven't heard any complaints yet :)

 * The other issue concerns selecting a maximum SSE level. Right now I
can pick some Arch, but the SSE level up to SSE3 (==PNI) is determined
by the probes. So even if I pick a PIII for example I end up with SSE3
support if the CPU supplies it. So far the trick I am using is to have
the SSE probe unconditionally return "FAILURE", so that for example I
get a SSE2 only ATLAS on a CPU with SSE3 or more. Obviously
performance will suck, but in case of Sage it is between "illegal
instructions" and working binaries, so performance  is something I can
sacrifice for that.

Is there a plan to make the SSE level selectable as a config option?

Cheers,

Michael

> **************************************************************************
> ** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
> **************************************************************************
>
> ------------------------------------------------------------------------------
> Open Source Business Conference (OSBC), March 24-25, 2009, San Francisco, CA
> -OSBC tackles the biggest issue in open source: Open Sourcing the Enterprise
> -Strategies to boost innovation and cut costs with open source participation
> -Receive a $600 discount off the registration fee with the source code: SFAD
> http://p.sf.net/sfu/XcvMzF8H
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[Michael Abshoff-3]

On Fri, Feb 20, 2009 at 1:52 PM, Michael Abshoff
<michael.abshoff@...> wrote:
> On Fri, Feb 20, 2009 at 1:10 PM, Clint Whaley <whaley@...> wrote:
>> Michael,

<SNIP>

> So unless your evil twin edited the page this got somehow lost.

It is actually still there right at the top of

 http://math-atlas.sourceforge.net/errata3.8.2.html

I missed it while I searched for it for some strange reason :)

Cheers,

Michael

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[Clint Whaley]

> So unless your evil twin edited the page this got somehow lost.
>It is actually still there right at the top of
> http://math-atlas.sourceforge.net/errata3.8.2.html
>I missed it while I searched for it for some strange reason :)

OK, I seem to have made all the other changes for that errata, so it looks
like I simply overlooked the case 6 change . . .

>Anyway, I am having two things I am currently interested in:
>
> * Itanium CPU identification. This CPU:

>processor  : 3
>vendor     : GenuineIntel
>arch       : IA-64
>family     : Itanium 2
>model      : 0
>revision   : 7
>archrev    : 0
>Running either RHEL 5 or SLES 10 is misidentified as a Itanium with
>standard ATLAS 3.8.3. I haven't poked around in the detection routines
>yet, but ATLAS might be missing a couple CPUids. For now I just force
>every Itanium to be an Itanium 2. Give the number of Itaniums in the
>wild I haven't heard any complaints yet :)

My guess is ATLAS is just parsing the cpuinfo file incorrectly (I don't
think archinfo_x86 works there, so we are stuck with the OS-specific tricks).
If you want to submit a patch on that, I'll be happy to fix . . .

> * The other issue concerns selecting a maximum SSE level. Right now I
>can pick some Arch, but the SSE level up to SSE3 (==PNI) is determined
>by the probes. So even if I pick a PIII for example I end up with SSE3
>>support if the CPU supplies it. So far the trick I am using is to have
>the SSE probe unconditionally return "FAILURE", so that for example I
>get a SSE2 only ATLAS on a CPU with SSE3 or more. Obviously
>performance will suck, but in case of Sage it is between "illegal
>instructions" and working binaries, so performance  is something I can
>sacrifice for that.
>
>Is there a plan to make the SSE level selectable as a config option?

Not only is there a plan, but it's been available since 3.8.0!  It's not
the easiest thing to grok, because one machine obviously can support many
vector extensions.  Here is the line from 'configure --help':
   -V #    # = ((1<<vecISA1) | (1<<vecISA2) | ... | (1<<vecISAN))

Now, since xprint_enums for some reason doens't print these values out,
I can oh so conveniently scope ATLAS/CONFIG/include/atlconf.h for:
   enum ISAEXT {ISA_None=0, ISA_AV, ISA_SSE3, ISA_SSE2, ISA_SSE1, ISA_3DNow};

Therefore, if I want no vector code at all, I throw '-V -0'; if I want
SSE2 & 1 but not 3, I throw (1<<3)+(1<<4) = 8+16=24, so '-V 24', and
bingo: no SSE3 even on a machine that does SSE3!

Cheers,
Clint

**************************************************************************
** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
**************************************************************************

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[Michael Abshoff-3]

On Fri, Feb 20, 2009 at 5:00 PM, Clint Whaley <whaley@...> wrote:

Hi Clint.

>> So unless your evil twin edited the page this got somehow lost.
>>It is actually still there right at the top of
>> http://math-atlas.sourceforge.net/errata3.8.2.html
>>I missed it while I searched for it for some strange reason :)
>
> OK, I seem to have made all the other changes for that errata, so it looks
> like I simply overlooked the case 6 change . . .

Well, I can understand how something like that can slip by on
occasion. I have done it often enough myself in Sage :)

>>Anyway, I am having two things I am currently interested in:
>>
>> * Itanium CPU identification. This CPU:
>
>>processor  : 3
>>vendor     : GenuineIntel
>>arch       : IA-64
>>family     : Itanium 2
>>model      : 0
>>revision   : 7
>>archrev    : 0
>>Running either RHEL 5 or SLES 10 is misidentified as a Itanium with
>>standard ATLAS 3.8.3. I haven't poked around in the detection routines
>>yet, but ATLAS might be missing a couple CPUids. For now I just force
>>every Itanium to be an Itanium 2. Give the number of Itaniums in the
>>wild I haven't heard any complaints yet :)
>
> My guess is ATLAS is just parsing the cpuinfo file incorrectly (I don't
> think archinfo_x86 works there, so we are stuck with the OS-specific tricks).
> If you want to submit a patch on that, I'll be happy to fix . . .

Ok, let me come up with a cleaner fix and post it to the support
tracker. I also never reliably got it to work that gcc ought to not
use "-m64" for gcc on Itanium even though that special case is in the
code after I corrected the detection problem, so I will look at that
again in the same go since right now I just insert a two line special
case to avoid setting any -mXX flag on Itanium.

>> * The other issue concerns selecting a maximum SSE level. Right now I
>>can pick some Arch, but the SSE level up to SSE3 (==PNI) is determined
>>by the probes. So even if I pick a PIII for example I end up with SSE3
>>>support if the CPU supplies it. So far the trick I am using is to have
>>the SSE probe unconditionally return "FAILURE", so that for example I
>>get a SSE2 only ATLAS on a CPU with SSE3 or more. Obviously
>>performance will suck, but in case of Sage it is between "illegal
>>instructions" and working binaries, so performance  is something I can
>>sacrifice for that.
>>
>>Is there a plan to make the SSE level selectable as a config option?
>
> Not only is there a plan, but it's been available since 3.8.0!  It's not
> the easiest thing to grok, because one machine obviously can support many
> vector extensions.  Here is the line from 'configure --help':
>   -V #    # = ((1<<vecISA1) | (1<<vecISA2) | ... | (1<<vecISAN))

Ahh, I grepped around and found the enum ISAEXT, but I did not connect
the dots here after staring at the help output of configure for a
while.

> Now, since xprint_enums for some reason doens't print these values out,
> I can oh so conveniently scope ATLAS/CONFIG/include/atlconf.h for:
>   enum ISAEXT {ISA_None=0, ISA_AV, ISA_SSE3, ISA_SSE2, ISA_SSE1, ISA_3DNow};
>
> Therefore, if I want no vector code at all, I throw '-V -0'; if I want
> SSE2 & 1 but not 3, I throw (1<<3)+(1<<4) = 8+16=24, so '-V 24', and
> bingo: no SSE3 even on a machine that does SSE3!

Cool, I will be giving this a try.

> Cheers,
> Clint

Cheers,

Michael

> **************************************************************************
> ** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
> **************************************************************************
>
> ------------------------------------------------------------------------------
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