BRx/ORx

[StevenASchroeder]

We are adding a 2MBx32 external flash to an MPC563 and would like it to
begin immediately after the internal flash, at 0x0008 0000.  The (high
16-bits) of BRx.BA would be 0x0008, but ORx.AM has caused confusion.

 

Do we consider the base address?  Then the address range of 0x0008 0000
to 0x0027 FFFF will need a mask of (high 16-bits) 0xFFC0, so active
addresses would actually be 0x0000 0000 to 0x003F FFFF.  (But addresses
with internal "stuff" will still go internal, yes?)

 

Or are we masking the address space of the part, 0x0000 0000 to 0x001F
FFFF, making the mask (high 16-bits) 0xFFE0?

 

Thanks,

Steve

 



[Non-text portions of this message have been removed]

[Dobbin Allan-r11834]

I'm rusty with this, so you'd want to get confirmation.
 
The AM is set independantly (sort of, see below) from the base address.
If you have a 2Mx32 i.e. 8Mbyte, you want the upper half of the OR
register set to FF8. For larger memories, use smaller numbers i.e. FF is
16Mbyte, FE is 32Mbyte, FC is 64Mbyte, etc. All the way up to 0 for 4G
and down to FFFF8 (all AM bits set) for 32Kbyte.
 
I said 'sort of' above because what is relevant is that the base should
be a multiple of the size.  Now this is the part I'm rusty on, so double
check this.  If I am correct, then you can't start an 8Mbyte at address
8_0000.  The lowest you could start would be 80_0000.  This makes sense
since the mask of FF80_0000 has masked off anything smaller than this in
the BA.
 
One last comment about sizes.  You quote a desired range of 8_0000
through 27_FFFF which is 2Mbytes.  Keep in mind that even with a 32-bit
bus, the MPC5xx treats address steps in bytes.  Yet when you say 2MBx32,
that sounds like you have a 2M bit deep by 32-bit wide which is 8Mbyte.
 
THere's bound to be a way to get what you want i.e. contiguous flash
space without sacrificing the size, but I'd need to think about it some
more.  Maybe use multiple chip selects through an AND gate, CS0 with
0.5M size starting at 8_0000, CS1 with 1M starting at 10_0000, etc.  Or
does this part allow you to remap the internal flash to an alternative
address?
 
- Allan
 
 

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of StevenASchroeder@...
Sent: Wednesday, September 12, 2007 11:30 AM
To: MPC500@...
Subject: [MPC500] BRx/ORx



We are adding a 2MBx32 external flash to an MPC563 and would like it to
begin immediately after the internal flash, at 0x0008 0000. The (high
16-bits) of BRx.BA would be 0x0008, but ORx.AM has caused confusion.

Do we consider the base address? Then the address range of 0x0008 0000
to 0x0027 FFFF will need a mask of (high 16-bits) 0xFFC0, so active
addresses would actually be 0x0000 0000 to 0x003F FFFF. (But addresses
with internal "stuff" will still go internal, yes?)

Or are we masking the address space of the part, 0x0000 0000 to 0x001F
FFFF, making the mask (high 16-bits) 0xFFE0?

Thanks,

Steve

[Non-text portions of this message have been removed]



 


[Non-text portions of this message have been removed]

[Dobbin Allan-r11834]

Maybe another way to do it.  Unless I'm mistaken, if you do an internal
access, you get internal memory.  So perhaps you can set the base
address to 0 which means you'd get internal flash for the first 0.5M and
external for the top 7.5M, you'd lose 0.5M of your flash though.  Again,
check this info is correct before implementing it.
 
- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of Dobbin Allan-r11834
Sent: Wednesday, September 12, 2007 12:44 PM
To: MPC500@...
Subject: RE: [MPC500] BRx/ORx



I'm rusty with this, so you'd want to get confirmation.

The AM is set independantly (sort of, see below) from the base address.
If you have a 2Mx32 i.e. 8Mbyte, you want the upper half of the OR
register set to FF8. For larger memories, use smaller numbers i.e. FF is
16Mbyte, FE is 32Mbyte, FC is 64Mbyte, etc. All the way up to 0 for 4G
and down to FFFF8 (all AM bits set) for 32Kbyte.

I said 'sort of' above because what is relevant is that the base should
be a multiple of the size. Now this is the part I'm rusty on, so double
check this. If I am correct, then you can't start an 8Mbyte at address
8_0000. The lowest you could start would be 80_0000. This makes sense
since the mask of FF80_0000 has masked off anything smaller than this in
the BA.

One last comment about sizes. You quote a desired range of 8_0000
through 27_FFFF which is 2Mbytes. Keep in mind that even with a 32-bit
bus, the MPC5xx treats address steps in bytes. Yet when you say 2MBx32,
that sounds like you have a 2M bit deep by 32-bit wide which is 8Mbyte.

THere's bound to be a way to get what you want i.e. contiguous flash
space without sacrificing the size, but I'd need to think about it some
more. Maybe use multiple chip selects through an AND gate, CS0 with
0.5M size starting at 8_0000, CS1 with 1M starting at 10_0000, etc. Or
does this part allow you to remap the internal flash to an alternative
address?

- Allan



________________________________

From: MPC500@... <mailto:MPC500%40yahoogroups.com>
[mailto:MPC500@... <mailto:MPC500%40yahoogroups.com> ] On
Behalf
Of StevenASchroeder@... <mailto:StevenASchroeder%40eaton.com>
Sent: Wednesday, September 12, 2007 11:30 AM
To: MPC500@... <mailto:MPC500%40yahoogroups.com>
Subject: [MPC500] BRx/ORx

We are adding a 2MBx32 external flash to an MPC563 and would like it to
begin immediately after the internal flash, at 0x0008 0000. The (high
16-bits) of BRx.BA would be 0x0008, but ORx.AM has caused confusion.

Do we consider the base address? Then the address range of 0x0008 0000
to 0x0027 FFFF will need a mask of (high 16-bits) 0xFFC0, so active
addresses would actually be 0x0000 0000 to 0x003F FFFF. (But addresses
with internal "stuff" will still go internal, yes?)

Or are we masking the address space of the part, 0x0000 0000 to 0x001F
FFFF, making the mask (high 16-bits) 0xFFE0?

Thanks,

Steve

[Non-text portions of this message have been removed]

[Non-text portions of this message have been removed]



 


[Non-text portions of this message have been removed]

[StevenASchroeder]

First, I goofed-our part is 2 MBytes, not 2Mx32.

 

As to basing it at 0x0008_0000, is that even possible.  A little
experimentation indicates that I may not be able to put external flash
into the "reserved for flash" area of the internal memory map.  I guess
that's implied by it being the internal memory map.  ;-)  If that is
correct, I think I got it-with the base address larger than the part
size, there is no overlap and no ambiguity.

 

Steve

 

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of Dobbin Allan-r11834
Sent: Wednesday, September 12, 2007 2:02 PM
To: MPC500@...
Subject: RE: [MPC500] BRx/ORx

 

Maybe another way to do it. Unless I'm mistaken, if you do an internal
access, you get internal memory. So perhaps you can set the base
address to 0 which means you'd get internal flash for the first 0.5M and
external for the top 7.5M, you'd lose 0.5M of your flash though. Again,
check this info is correct before implementing it.

- Allan

________________________________

From: MPC500@... <mailto:MPC500%40yahoogroups.com>
[mailto:MPC500@... <mailto:MPC500%40yahoogroups.com> ] On
Behalf
Of Dobbin Allan-r11834
Sent: Wednesday, September 12, 2007 12:44 PM
To: MPC500@... <mailto:MPC500%40yahoogroups.com>
Subject: RE: [MPC500] BRx/ORx

I'm rusty with this, so you'd want to get confirmation.

The AM is set independantly (sort of, see below) from the base address.
If you have a 2Mx32 i.e. 8Mbyte, you want the upper half of the OR
register set to FF8. For larger memories, use smaller numbers i.e. FF is
16Mbyte, FE is 32Mbyte, FC is 64Mbyte, etc. All the way up to 0 for 4G
and down to FFFF8 (all AM bits set) for 32Kbyte.

I said 'sort of' above because what is relevant is that the base should
be a multiple of the size. Now this is the part I'm rusty on, so double
check this. If I am correct, then you can't start an 8Mbyte at address
8_0000. The lowest you could start would be 80_0000. This makes sense
since the mask of FF80_0000 has masked off anything smaller than this in
the BA.

One last comment about sizes. You quote a desired range of 8_0000
through 27_FFFF which is 2Mbytes. Keep in mind that even with a 32-bit
bus, the MPC5xx treats address steps in bytes. Yet when you say 2MBx32,
that sounds like you have a 2M bit deep by 32-bit wide which is 8Mbyte.

THere's bound to be a way to get what you want i.e. contiguous flash
space without sacrificing the size, but I'd need to think about it some
more. Maybe use multiple chip selects through an AND gate, CS0 with
0.5M size starting at 8_0000, CS1 with 1M starting at 10_0000, etc. Or
does this part allow you to remap the internal flash to an alternative
address?

- Allan

________________________________

From: MPC500@... <mailto:MPC500%40yahoogroups.com>
<mailto:MPC500%40yahoogroups.com>
[mailto:MPC500@... <mailto:MPC500%40yahoogroups.com>
<mailto:MPC500%40yahoogroups.com> ] On
Behalf
Of StevenASchroeder@... <mailto:StevenASchroeder%40eaton.com>
<mailto:StevenASchroeder%40eaton.com>
Sent: Wednesday, September 12, 2007 11:30 AM
To: MPC500@... <mailto:MPC500%40yahoogroups.com>
<mailto:MPC500%40yahoogroups.com>
Subject: [MPC500] BRx/ORx

We are adding a 2MBx32 external flash to an MPC563 and would like it to
begin immediately after the internal flash, at 0x0008 0000. The (high
16-bits) of BRx.BA would be 0x0008, but ORx.AM has caused confusion.

Do we consider the base address? Then the address range of 0x0008 0000
to 0x0027 FFFF will need a mask of (high 16-bits) 0xFFC0, so active
addresses would actually be 0x0000 0000 to 0x003F FFFF. (But addresses
with internal "stuff" will still go internal, yes?)

Or are we masking the address space of the part, 0x0000 0000 to 0x001F
FFFF, making the mask (high 16-bits) 0xFFE0?

Thanks,

Steve

[Non-text portions of this message have been removed]

[Non-text portions of this message have been removed]

[Non-text portions of this message have been removed]

 



[Non-text portions of this message have been removed]