Bypass capacitor question

[William "Chops" Westfield]

Speaking of ceramic caps...

A 0.1uF cap has long been the standard for power supply bypass  
capacitors of most ICs.  Occasionally you'd see smaller values  
(0.01uF) in higher frequency designs.

As I understand it, the idea was that smaller value caps had "better"  
characteristics such a lead and internal inductance, ESR, and so on.  
While bigger caps had, well, more capacitance.  0.1uF was the "sweet  
spot" for most apps.

So, that was all about a generation ago.  TTL and ceramic disk caps.  
Nowadays, I wonder if these rules of thumb are obsolete.  It's hard  
for me to imagine that a 0.1uF 0805 SMT ceramic cap has much different  
non-capacitance features from a 10uF 0805 SMT ceramic cap (different  
dielectric, different max voltage, yeah, but those are less relevant  
to bypass, right?)  The situation is similar for leaded multilayer  
ceramic caps (SMT cap with leads, pretty much, eh?)

So is there some new reason for carefully picking bypass cap values  
(modern CPUs and certain chips get very picky, but is that more of  
"we're sure that this works" rather than "this is actually what is  
required"?)  Is more capacitance better, within a certain smt cap  
size, as long as rated voltage stays high enough?  Are the exotic  
dielectrics that permit 100uF ceramic caps (ok, bigger than 0805!)  
subject to odd physics that makes them poor bypass caps?  What ARE the  
new rules, or new concerns, now that lead-length and long spools of  
foil are no longer players?

Thanks
Bill W

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[Sean Breheny]

Hi Bill,

I cannot give you a complete answer but I do have a few items that I
learned recently:

1) The "miracle" multi-layer ceramic chip capacitors which have >1uF
capacitance do have some strange behavior. First of all, their
capacitance is given for 0V DC bias. It is often significantly lower
as you approach their max rated voltage. For example, I tested some
2.2uF, 100V, 1210 and 1810 size MLCC caps from several manufacturers
(Taiyo Yuden, Murata, Kemet). All of them showed a capacitance of >2uF
at 0V bias, but at 50V, some were as low as 1.5uF. They also are
significantly piezoelectric. If you put an audio frequency current
through them, you can hear them like little speakers. Also, the
capacitance change due to DC bias is somewhat time dependent. For
example, if you take one of these caps and measure its capacitance at
0V, you may get 2uF. Then, you apply 50V, and get 1uF. Now, you
suddenly discharge the capacitor to 0V and measure its capacitance
again. It might be 1.5uF and then slowly (over the course of minutes)
drift back down to its original 2uF capacitance.

2) I think that it is still true that, for a fixed case size, there
will be a range of capacitance which has the lowest ESR and ESL
(effective series resistance and inductance). For one thing, the
higher the capacitance per volume, it is likely that they have to
sacrifice metalization thickness and have a longer average path from
end contact to all parts of the plates.

Sean

On Mon, Oct 12, 2009 at 1:08 PM, William "Chops" Westfield
<westfw@...> wrote:

> Speaking of ceramic caps...
>
> A 0.1uF cap has long been the standard for power supply bypass
> capacitors of most ICs.  Occasionally you'd see smaller values
> (0.01uF) in higher frequency designs.
>
> As I understand it, the idea was that smaller value caps had "better"
> characteristics such a lead and internal inductance, ESR, and so on.
> While bigger caps had, well, more capacitance.  0.1uF was the "sweet
> spot" for most apps.
>
> So, that was all about a generation ago.  TTL and ceramic disk caps.
> Nowadays, I wonder if these rules of thumb are obsolete.  It's hard
> for me to imagine that a 0.1uF 0805 SMT ceramic cap has much different
> non-capacitance features from a 10uF 0805 SMT ceramic cap (different
> dielectric, different max voltage, yeah, but those are less relevant
> to bypass, right?)  The situation is similar for leaded multilayer
> ceramic caps (SMT cap with leads, pretty much, eh?)
>
> So is there some new reason for carefully picking bypass cap values
> (modern CPUs and certain chips get very picky, but is that more of
> "we're sure that this works" rather than "this is actually what is
> required"?)  Is more capacitance better, within a certain smt cap
> size, as long as rated voltage stays high enough?  Are the exotic
> dielectrics that permit 100uF ceramic caps (ok, bigger than 0805!)
> subject to odd physics that makes them poor bypass caps?  What ARE the
> new rules, or new concerns, now that lead-length and long spools of
> foil are no longer players?
>
> Thanks
> Bill W
>
> --
> http://www.piclist.com PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

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[Olin Lathrop]

William Chops" Westfield" wrote:
> A 0.1uF cap has long been the standard for power supply bypass
> capacitors of most ICs.  Occasionally you'd see smaller values
> (0.01uF) in higher frequency designs.

Yes, back in the pleistocene.  I've been using 1uF SMD ceramics as the
standard bypass caps for a bunch of years now.  Look at the datasheet of one
of these and compare it to a 100nF cap.  The high end frequency responses
aren't all that different, and definitely better than the 100nF leaded caps
of the dark ages.

Up to PIC-level digital circuits, just use a 1uF SMD cap and be done with
it.  If you've got something special RF or otherwise high frequency going
on, then you still have to look at the datasheets of specific model caps.
You should still put the 1uF near the chip at the common power and ground
feed points, but then possibly use smaller values with higher frequency
capability for local decoupling within the private power/ground of the
specific chip.

In one design I was envolved with a few years ago, we used specific 100pF
caps on each of the power pins of a RF chip because those had the lowest
impedence at the RF frequency that we could find.  In that case we also
isolated each power lead with 10 ohm resistors, and there were larger caps
at the common feed point with a series inductor and even larger caps on the
other side of the inductor.  Sometimes it helps to think of the power and
ground feeds to high frequency circuits as a tree structure, with lower and
high frequency caps needed at the leaves.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
[phone].  Gold level PIC consultants since 2000.
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[Alan Smith-10]

Bypass caps also need to take into consideration of the switching frequencies of the devices.  Xilinx has had some really good papers on this, targeting the FPGA design of course, but this is a good starting point.  Back in the day, sprinkling 0.1uF on each device was deemed sufficient and probably is for most PIC based designs.

http://ftp.cse.sc.edu/jdavis/csce613/Xilinx/Vertex-AppNotes&Sample%20Code/xapp158.pdf

--- On Mon, 10/12/09, William "Chops" Westfield <westfw@...> wrote:

> From: William "Chops" Westfield <westfw@...>
> Subject: [EE] Bypass capacitor question
> To: "Microcontroller discussion list - Public." <piclist@...>
> Date: Monday, October 12, 2009, 10:08 AM
> Speaking of ceramic caps...
>
> A 0.1uF cap has long been the standard for power supply
> bypass 
> capacitors of most ICs.  Occasionally you'd see
> smaller values 
> (0.01uF) in higher frequency designs.
>
> As I understand it, the idea was that smaller value caps
> had "better" 
> characteristics such a lead and internal inductance, ESR,
> and so on.   
> While bigger caps had, well, more capacitance.  0.1uF
> was the "sweet 
> spot" for most apps.
>
> So, that was all about a generation ago.  TTL and
> ceramic disk caps.   
> Nowadays, I wonder if these rules of thumb are
> obsolete.  It's hard 
> for me to imagine that a 0.1uF 0805 SMT ceramic cap has
> much different 
> non-capacitance features from a 10uF 0805 SMT ceramic cap
> (different 
> dielectric, different max voltage, yeah, but those are less
> relevant 
> to bypass, right?)  The situation is similar for
> leaded multilayer 
> ceramic caps (SMT cap with leads, pretty much, eh?)
>
> So is there some new reason for carefully picking bypass
> cap values 
> (modern CPUs and certain chips get very picky, but is that
> more of 
> "we're sure that this works" rather than "this is actually
> what is 
> required"?)  Is more capacitance better, within a
> certain smt cap 
> size, as long as rated voltage stays high enough?  Are
> the exotic 
> dielectrics that permit 100uF ceramic caps (ok, bigger than
> 0805!) 
> subject to odd physics that makes them poor bypass
> caps?  What ARE the 
> new rules, or new concerns, now that lead-length and long
> spools of 
> foil are no longer players?
>
> Thanks
> Bill W
>
> --
> http://www.piclist.com PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

     

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[William "Chops" Westfield]

On Oct 12, 2009, at 11:01 AM, alan smith wrote:

>
> http://ftp.cse.sc.edu/jdavis/csce613/Xilinx/Vertex-AppNotes&Sample%20Code/xapp158.pdf

Yes, but this is from 2001 and they divide caps into three categories:

>> Proper placement is very important for high-frequency capacitors  
>> (0.1uF to 0.001uF low-inductance ceramic chip). It is less  
>> important for middle-frequency capacitors (47uF to 100uF tantalum),  
>> and even less important for low-frequency capacitors (470uF to  
>> 3300uF).

What I'm most curious about is the ceramic chip caps 0.1uF < C < 47uF  
that they don't talk about.   They're still small; are they still high-
frequency? (in general; I suppose I could look at individual data  
sheets for specifics.)  If I sprinkle 10uF ceramics where there used  
to be 0.1uF ceramics, do I relax the needs for the middle-freq caps?  
Or have the capacitance of "small" ceramics just barely kept pace with  
the increased power demands of most chips?

BillW

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