CRC generator

[anulekha.aeranki]

Hi,
I need a configurable input data width, 32 bit CRC generator.
I downloaded "ultimate_crc" from open cores. But one file down load
says "wb_tb_pack.vhd is reused from the spdif project. Fetch the latest
revision of this file from there." I am not able to find what is this spdif
project. Please help me in finiding this file.
Thanks
Anulekha

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http://www.opencores.org/mailman/listinfo/cores

[Ian Burns]

Hi

Have a look at the free one at

http://www.think-silicon.com/ipgenius.php?module=CRC_generator

Regards
Ian.

anulekha.aeranki@... wrote:

> Hi,
> I need a configurable input data width, 32 bit CRC generator.
> I downloaded "ultimate_crc" from open cores. But one file down load
> says "wb_tb_pack.vhd is reused from the spdif project. Fetch the latest
> revision of this file from there." I am not able to find what is this spdif
> project. Please help me in finiding this file.
> Thanks
> Anulekha
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>  

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Umair Siddiqui]

http://www.easics.com/webtools/crctool

On Thu, Sep 25, 2008 at 7:44 AM,  <anulekha.aeranki@...> wrote:

> Hi,
> I need a configurable input data width, 32 bit CRC generator.
> I downloaded "ultimate_crc" from open cores. But one file down load
> says "wb_tb_pack.vhd is reused from the spdif project. Fetch the latest
> revision of this file from there." I am not able to find what is this spdif
> project. Please help me in finiding this file.
> Thanks
> Anulekha
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[iztok.jeras]

you can modify this code, it is very compact, but I have not tested it:

//Calculates CRC7
module crc #(
  parameter integer   len  = 7;
  parameter [len-1:0] poly = 7'b0001001;
)(
  input  wire          rst;
  input  wire          clk;
  input  wire          clr;
  input  wire          din;
  input  wire          ena;
  output reg [len-1:0] crc;
);

always @ (posedge clk, posedge rst) begin
if (rst)           crc <= {len{1'b0}};
else begin
 if (clr)          crc <= {len{1'b0}};
 else if (ena)  crc <= {crc[len-1:0], 1'b0} ^ (poly &
{len{din^crc[len-1]}});
end

endmodule

----- Original Message -----
From: anulekha.aeranki at wipro.com<anulekha.aeranki@w...>
To:
Date: Thu Sep 25 04:44:14 CEST 2008
Subject: [oc] CRC generator

> Hi,
> I need a configurable input data width, 32 bit CRC generator.
> I downloaded "ultimate_crc" from open cores. But one file
> down load
> says "wb_tb_pack.vhd is reused from the spdif project. Fetch
> the latest
> revision of this file from there." I am not able to find what
> is this spdif
> project. Please help me in finiding this file.
> Thanks
> Anulekha
>
>

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http://www.opencores.org/mailman/listinfo/cores

[OutputLogic]

There is an online tool that generates CRC code for Verilog or VHDL: OutputLogic.com. It has configurable data and polynomial width.
Hope that helps.

anulekha.aeranki wrote:

Hi,
I need a configurable input data width, 32 bit CRC generator.
I downloaded "ultimate_crc" from open cores. But one file down load
says "wb_tb_pack.vhd is reused from the spdif project. Fetch the latest
revision of this file from there." I am not able to find what is this spdif
project. Please help me in finiding this file.
Thanks
Anulekha

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores