Harvard caches

I am moving some code from a MCF537x coldfire, which had a unified cache, to a MCF547x which has separate instruction and data caches.

My code has lots of tables declared as const so that they go into the read only text section in flash, rather than the initialised data section in RAM. Does this mean that all my table accesses will miss the cache because they will be in the range for the instruction cache, but are not instruction fetches?

Similarly I have a few instructions in my bss section, mainly jump instruction to redirect interrupts to the relevent device driver. Am I right in thinking that these will all be cache misses as well because they will be in the range of the data cache but are actually instruction fetches?

Is there any way I can set up the caches to emulate a unified cache or do I have to rewrite all my code?

Another thing I don't understand is the two 4K SRAMs. The manual says I need to specifiy whether they are connected to the instruction bus or the data bus,. but it also gives RAMBAR address space settings for both code and data. Can I mix code and data in these RAMS, and if so, which bus do I specify and how does it work if they are one the wrong bus for the access?

TIA, Chris
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