Help on Makefile

Code:

all : $(SOURCES)
        $(CC) $(CFLAGS) -o $(OBJECTS) $(SOURCES)

Code:

SOURCES = libiberty/alloca.c \
                libiberty/argv.c \
                libiberty/asprintf.c \
                libiberty/atexit.c \
       
...

Code:

OBJECTS = debug/libiberty/alloca.o  \
                debug/libiberty/argv.o   \
                debug/libiberty/asprintf.o  \
                debug/libiberty/atexit.o  \
                debug/libiberty/basename.o  \
                debug/libiberty/bcmp.o \
                debug/libiberty/bcopy.o \
                debug/libiberty/bsearch.o \

if i have such a build rule as this is, the whole OBJECTS and SOURCES will be compiled in a single batch. How do I compile them separately? I have googled, but already spent too much time on it

Thanks
Jack