I2C vhdl

[metanoya]

Hi

Can anyone please help me?  I need to implement an i2c bus for a project.  I am using a dsp to send commands to registers in an fpga from where I will control the i2c.  I am using an existing reference design for my development board.  Can anyone please help me with something?  I got the documentation for the i2c master core written by R. Herveille.  I know that I need to write to registers to read and write, but I don't know how to access those registers using the reference design.  In other words, I just need to know if anyone can help me to integrate the i2c controller using the reference design?

Thank you.

Sebastiaan Heunis

[Richard Herveille]

Yeah sure.
First of all which version of the core are you using?
There's an old (simple_i2c) and the i2c_master core.
Use the latter; map it into the DSP's memory range and access it as though
it's a memory device.
Read the documentation for the register addresses.

Richard


-----Original Message-----
From: cores-bounces@... [mailto:cores-bounces@...] On
Behalf Of metanoya
Sent: Monday, August 20, 2007 10:08 AM
To: cores@...
Subject: [oc] I2C vhdl


Hi

Can anyone please help me?  I need to implement an i2c bus for a project.  I
am using a dsp to send commands to registers in an fpga from where I will
control the i2c.  I am using an existing reference design for my development
board.  Can anyone please help me with something?  I got the documentation
for the i2c master core written by R. Herveille.  I know that I need to
write to registers to read and write, but I don't know how to access those
registers using the reference design.  In other words, I just need to know
if anyone can help me to integrate the i2c controller using the reference
design?

Thank you.

Sebastiaan Heunis
--
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http://www.nabble.com/I2C-vhdl-tf4297287.html#a12231686
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[metanoya]

Richard

Thanks, I would just please like to know one or two things.  The STB_I input, CYC_I input, ACK_O output, INTA_O output, the last part where SDA and SCL is tristated and the two resets.  How exactly does the STB_I and CYC_I inputs work?  Is ACK_O asserted after every write to a register?  Is the INTA_O output only used when interrupts are enabled?  Where do I insert the tristate buffers for SDA and SCL and lastly, where do I tie the unused reset to a negated state?  Can I do that in the port declaration?

Thank you.
 

Richard Herveille wrote:

Yeah sure.
First of all which version of the core are you using?
There's an old (simple_i2c) and the i2c_master core.
Use the latter; map it into the DSP's memory range and access it as though
it's a memory device.
Read the documentation for the register addresses.

Richard


-----Original Message-----
From: [e-mail] [mailto:[e-mail]] On
Behalf Of metanoya
Sent: Monday, August 20, 2007 10:08 AM
To: [e-mail]
Subject: [oc] I2C vhdl


Hi

Can anyone please help me?  I need to implement an i2c bus for a project.  I
am using a dsp to send commands to registers in an fpga from where I will
control the i2c.  I am using an existing reference design for my development
board.  Can anyone please help me with something?  I got the documentation
for the i2c master core written by R. Herveille.  I know that I need to
write to registers to read and write, but I don't know how to access those
registers using the reference design.  In other words, I just need to know
if anyone can help me to integrate the i2c controller using the reference
design?

Thank you.

Sebastiaan Heunis
--
View this message in context:
http://www.nabble.com/I2C-vhdl-tf4297287.html#a12231686
Sent from the OpenCores - IP Cores mailing list archive at Nabble.com.

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http://www.opencores.org/mailman/listinfo/cores

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http://www.opencores.org/mailman/listinfo/cores