I2c and Avalon Bus

Hello all,

I'm currently working on opencores I2C master (VHDL version) to
the NIOS 2 processor via the Avalon bus.(Stratix II)
There is an older post about this subject but I can't resolved my problem.

So I've used i2c_master_top_avalon.vhd and I've created a wrapper to use this component with Avalon bus oc_i2c_master.vhd 

I've configured the component
 

and attached this to a NIOS 2 processor


I've assigned Sda ans Scl


So I use I2c to configure a video camera (http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/jzs3_da65/C3088.pdf ) but  i can't set this !!

I think the problem is it can't recognize the slave (video camera), in fact when I write a value into the register of the video camera I'm waiting for the TIP flag and RxACK flag but the RXACK always stay at '1'...

At start I've thought there was a problem with the slave adress but i've tested all the values between 0 and 255 with no success !!!

An exemple of my code to write into slave's register :

// address : address of the slave
// reg : address of the slave's register
// data : value  wich write in the slave's register

void i2c_write(unsigned char address, unsigned char reg, unsigned char data) {
 
// write address
  IOWR_I2C_TXR(address);
  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK );
  i2c_wait_tip();
  i2c_rxack();
 
  // write register address
  IOWR_I2C_TXR(reg);
  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK);
  i2c_wait_tip();
  i2c_rxack();

  // write data
  IOWR_I2C_TXR(data);
  IOWR_I2C_CR(OC_I2C_WR | OC_I2C_STO);
  i2c_wait_tip();
  i2c_rxack();
}

void i2c_rxack(void){
 while ((IORD_I2C_SR & OC_I2C_RXACK)> 0 ) {}
 }

I've initialized CTR (0x80) before write into slave's register

Can I have some help, please ?

Thank you very much

Regards

[Richard Herveille]

Can you hook up an oscilloscope and see any activity on SCL/SDA??

Richard



-----Original Message-----
From: cores-bounces@... [mailto:cores-bounces@...] On
Behalf Of K@nt
Sent: 29 May 2008 10:53
To: cores@...
Subject: [oc] I2c and Avalon Bus


Hello all,

I'm currently working on opencores I2C master (VHDL version) to
the NIOS 2 processor via the Avalon bus.(Stratix II)
There is an older post about this subject but I can't resolved my problem.

So I've used i2c_master_top_avalon.vhd and I've created a wrapper to use
this component with Avalon bus
http://www.nabble.com/file/p17530366/oc_i2c_master.vhd oc_i2c_master.vhd  

I've configured the component(
http://www.nabble.com/file/p17530366/component.jpg ) and attached this to a
NIOS 2 processor.( http://www.nabble.com/file/p17530366/sopc.jpg )

I've assigned Sda ans Scl  http://www.nabble.com/file/p17530366/pin.jpg 

So I use I2c to configure a video camera (
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/jzs3_
da65/C3088.pdf
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/jzs3_
da65/C3088.pdf
) but  i can't set this !!

I think the problem is it can't recognize the slave (video camera), in fact
when I write a value into the register of the video camera I'm waiting for
the TIP flag and RxACK flag but the RXACK always stay at '1'...

At start I've thought there was a problem with the slave adress but i've
tested all the values between 0 and 255 with no success !!!

An exemple of my code to write into slave's register :

// address : address of the slave
// reg : address of the slave's register
// data : value  wich write in the slave's register

void i2c_write(unsigned char address, unsigned char reg, unsigned char data)
{
 
// write address
  IOWR_I2C_TXR(address);
  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK );
  i2c_wait_tip();
  i2c_rxack();
 
  // write register address
  IOWR_I2C_TXR(reg);
  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK);
  i2c_wait_tip();
  i2c_rxack();

  // write data
  IOWR_I2C_TXR(data);
  IOWR_I2C_CR(OC_I2C_WR | OC_I2C_STO);
  i2c_wait_tip();
  i2c_rxack();
}

void i2c_rxack(void){
 while ((IORD_I2C_SR & OC_I2C_RXACK)> 0 ) {}
 }

I've initialized CTR (0x80) before write into slave's register

Can I have some help, please ?

Thank you very much

Regards
--
View this message in context:
http://www.nabble.com/I2c-and-Avalon-Bus-tp17530366p17530366.html
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Hello,

I use Signal Tap II Logic Analyser in Quartus, and I see a "normal" activity on SCl and SDA. I chose 10khz for Scl clock.

TIP flag work, and Start and Stop signals are detected. I've just a problem with RxACK flag.

I've defined : OC_I2C_ACK (1<<3)
 
Is there an other way to check communication between I2C Master and the slave ?

Thank you

Regards

Richard Herveille wrote:

Can you hook up an oscilloscope and see any activity on SCL/SDA??

Richard


-----Original Message-----
From: [e-mail] [mailto:[e-mail]] On
Behalf Of K@nt
Sent: 29 May 2008 10:53
To: [e-mail]
Subject: [oc] I2c and Avalon Bus


Hello all,

I'm currently working on opencores I2C master (VHDL version) to
the NIOS 2 processor via the Avalon bus.(Stratix II)
There is an older post about this subject but I can't resolved my problem.

So I've used i2c_master_top_avalon.vhd and I've created a wrapper to use
this component with Avalon bus
http://www.nabble.com/file/p17530366/oc_i2c_master.vhd oc_i2c_master.vhd  

I've configured the component(
http://www.nabble.com/file/p17530366/component.jpg ) and attached this to a
NIOS 2 processor.( http://www.nabble.com/file/p17530366/sopc.jpg )

I've assigned Sda ans Scl  http://www.nabble.com/file/p17530366/pin.jpg 

So I use I2c to configure a video camera (
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/jzs3_
da65/C3088.pdf
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/jzs3_
da65/C3088.pdf
) but  i can't set this !!

I think the problem is it can't recognize the slave (video camera), in fact
when I write a value into the register of the video camera I'm waiting for
the TIP flag and RxACK flag but the RXACK always stay at '1'...

At start I've thought there was a problem with the slave adress but i've
tested all the values between 0 and 255 with no success !!!

An exemple of my code to write into slave's register :

// address : address of the slave
// reg : address of the slave's register
// data : value  wich write in the slave's register

void i2c_write(unsigned char address, unsigned char reg, unsigned char data)
{
 
// write address
  IOWR_I2C_TXR(address);
  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK );
  i2c_wait_tip();
  i2c_rxack();
 
  // write register address
  IOWR_I2C_TXR(reg);
  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK);
  i2c_wait_tip();
  i2c_rxack();

  // write data
  IOWR_I2C_TXR(data);
  IOWR_I2C_CR(OC_I2C_WR | OC_I2C_STO);
  i2c_wait_tip();
  i2c_rxack();
}

void i2c_rxack(void){
 while ((IORD_I2C_SR & OC_I2C_RXACK)> 0 ) {}
 }

I've initialized CTR (0x80) before write into slave's register

Can I have some help, please ?

Thank you very much

Regards
--
View this message in context:
http://www.nabble.com/I2c-and-Avalon-Bus-tp17530366p17530366.html
Sent from the OpenCores - IP Cores mailing list archive at Nabble.com.

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[jonathan.butzine]

Before using the oscilloscope, you may want to use signal tap to
determine if your signals (SCL, SDA) look correct coming out of your
SOPC builder system.
Then check your signal hook up from your SOPC Builder system to the
pins.  You need to hook up the SDA signal directly from SOPC Builder to
the pin because SDA is a bidirectional line and the tri-state handling is
done in the core.

----- Original Message -----
From: Richard Herveille<richard@h...>
To:
Date: Thu May 29 14:47:49 CEST 2008
Subject: [oc] I2c and Avalon Bus

> Can you hook up an oscilloscope and see any activity on SCL/SDA??
>
> Richard
>
> -----Original Message-----
> From: cores-bounces at opencores.org [mailto:cores-bounces at
> opencores.org] On
> Behalf Of K at nt
> Sent: 29 May 2008 10:53
> To: cores at opencores.org
> Subject: [oc] I2c and Avalon Bus
> Hello all,
> I'm currently working on opencores I2C master (VHDL version) to
> the NIOS 2 processor via the Avalon bus.(Stratix II)
> There is an older post about this subject but I can't resolved my
> problem.
> So I've used i2c_master_top_avalon.vhd and I've created a wrapper
> to use
> this component with Avalon bus
> http://www.nabble.com/file/p17530366/oc_i2c_master.vhd 
> oc_i2c_master.vhd
> I've configured the component(
> http://www.nabble.com/file/p17530366/component.jpg ) and

attached
> this to a
> NIOS 2 processor.( http://www.nabble.com/file/p17530366/sopc.jpg )
> I've assigned Sda ans Scl
> http://www.nabble.com/file/p17530366/pin.jpg 
> So I use I2c to configure a video camera (
>
>
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/j
zs3_
> da65/C3088.pdf
>
>
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/j
zs3_

> da65/C3088.pdf
> ) but i can't set this !!
> I think the problem is it can't recognize the slave (video camera),
> in fact
> when I write a value into the register of the video camera I'm
> waiting for
> the TIP flag and RxACK flag but the RXACK always stay at '1'...
> At start I've thought there was a problem with the slave adress but
> i've
> tested all the values between 0 and 255 with no success !!!
> An exemple of my code to write into slave's register :
> // address : address of the slave
> // reg : address of the slave's register
> // data : value wich write in the slave's register
> void i2c_write(unsigned char address, unsigned char reg, unsigned
> char data)
> {
>
> // write address
>  IOWR_I2C_TXR(address);
>  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK );
>  i2c_wait_tip();
>  i2c_rxack();
>
>  // write register address
>  IOWR_I2C_TXR(reg);
>  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK);
>  i2c_wait_tip();
>  i2c_rxack();
>  // write data
>  IOWR_I2C_TXR(data);
>  IOWR_I2C_CR(OC_I2C_WR | OC_I2C_STO);
>  i2c_wait_tip();
>  i2c_rxack();
> }
> void i2c_rxack(void){
>  while ((IORD_I2C_SR & OC_I2C_RXACK)> 0 ) {}
>  }
> I've initialized CTR (0x80) before write into slave's register
> Can I have some help, please ?
> Thank you very much
> Regards
> --
> View this message in context:
> http://www.nabble.com/I2c-and-Avalon-Bus-

tp17530366p17530366.html
> Sent from the OpenCores - IP Cores mailing list archive at
> Nabble.com.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores 
>
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

Hello,

SCL and SDA look correct. Start ans stop signals is ok.. But it's not very easy to check the data between start and stop signals.

Maybe my interface Wisbone/Avalon doesn't work properly... Is there an interface that works properly?

Thank you

jonathan.butzine wrote:

Before using the oscilloscope, you may want to use signal tap to
determine if your signals (SCL, SDA) look correct coming out of your
SOPC builder system.
Then check your signal hook up from your SOPC Builder system to the
pins.  You need to hook up the SDA signal directly from SOPC Builder to
the pin because SDA is a bidirectional line and the tri-state handling is
done in the core.

----- Original Message -----
From: Richard Herveille<richard@h...>
To:
Date: Thu May 29 14:47:49 CEST 2008
Subject: [oc] I2c and Avalon Bus

> Can you hook up an oscilloscope and see any activity on SCL/SDA??
>
> Richard
>
> -----Original Message-----
> From: cores-bounces at opencores.org [mailto:cores-bounces at
> opencores.org] On
> Behalf Of K at nt
> Sent: 29 May 2008 10:53
> To: cores at opencores.org
> Subject: [oc] I2c and Avalon Bus
> Hello all,
> I'm currently working on opencores I2C master (VHDL version) to
> the NIOS 2 processor via the Avalon bus.(Stratix II)
> There is an older post about this subject but I can't resolved my
> problem.
> So I've used i2c_master_top_avalon.vhd and I've created a wrapper
> to use
> this component with Avalon bus
> http://www.nabble.com/file/p17530366/oc_i2c_master.vhd 
> oc_i2c_master.vhd
> I've configured the component(
> http://www.nabble.com/file/p17530366/component.jpg ) and
attached
> this to a
> NIOS 2 processor.( http://www.nabble.com/file/p17530366/sopc.jpg )
> I've assigned Sda ans Scl
> http://www.nabble.com/file/p17530366/pin.jpg 
> So I use I2c to configure a video camera (
>
>
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/j
zs3_
> da65/C3088.pdf
>
>
http://ltc.cit.cornell.edu/courses/ee476/FinalProjects/s2006/jzs3_da65/j
zs3_
> da65/C3088.pdf
> ) but i can't set this !!
> I think the problem is it can't recognize the slave (video camera),
> in fact
> when I write a value into the register of the video camera I'm
> waiting for
> the TIP flag and RxACK flag but the RXACK always stay at '1'...
> At start I've thought there was a problem with the slave adress but
> i've
> tested all the values between 0 and 255 with no success !!!
> An exemple of my code to write into slave's register :
> // address : address of the slave
> // reg : address of the slave's register
> // data : value wich write in the slave's register
> void i2c_write(unsigned char address, unsigned char reg, unsigned
> char data)
> {
>
> // write address
>  IOWR_I2C_TXR(address);
>  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK );
>  i2c_wait_tip();
>  i2c_rxack();
>
>  // write register address
>  IOWR_I2C_TXR(reg);
>  IOWR_I2C_CR(OC_I2C_STA | OC_I2C_WR | OC_I2C_ACK);
>  i2c_wait_tip();
>  i2c_rxack();
>  // write data
>  IOWR_I2C_TXR(data);
>  IOWR_I2C_CR(OC_I2C_WR | OC_I2C_STO);
>  i2c_wait_tip();
>  i2c_rxack();
> }
> void i2c_rxack(void){
>  while ((IORD_I2C_SR & OC_I2C_RXACK)> 0 ) {}
>  }
> I've initialized CTR (0x80) before write into slave's register
> Can I have some help, please ?
> Thank you very much
> Regards
> --
> View this message in context:
> http://www.nabble.com/I2c-and-Avalon-Bus-
tp17530366p17530366.html
> Sent from the OpenCores - IP Cores mailing list archive at
> Nabble.com.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores 
>
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores