IRA is not looking into the predicates ?

[Mohamed Shafi]

Hi,

I am doing a port for a 32bit target in GCC 4.4.0. The target does not
have support for symbolic address in QImode for load operations. In
order to do this what i have done is in define_expand for moveqi
reject symbolic address it they come in source operands and i have
also written a predicate for *moveqi_internal to reject such cases.
But i get the following ICE:

 insn does not satisfy its constraints:
(insn 24 5 6 2 ice4.c:4 (set (reg:QI 17 r1)
        (mem/c/i:QI (symbol_ref:SI ("s") [flags 0x2] <var_decl
0xb7bfd000 s>) [0 s+0 S1 A32])) 0 {*movqi_internal} (nil))


From ice4.c.172r.ira

(insn 24 5 6 2 ice4.c:4 (set (reg:QI 17 r1)
        (mem/c/i:QI (symbol_ref:SI ("s") [flags 0x2] <var_decl
0xb7bfd000 s>) [0 s+0 S1 A32])) 0 {*movqi_internal} (nil))

(insn 6 24 7 2 ice4.c:4 (set (reg:QI 16 r0 [62])
        (plus:QI (reg:QI 17 r1)
            (const_int -100 [0xffffff9c]))) 16 {addqi3} (nil))

From ice4.c.168r.asmcons

(insn 5 2 6 2 ice4.c:4 (set (reg:SI 61 [ s ])
        (mem/c/i:SI (symbol_ref:SI ("s") [flags 0x2] <var_decl
0xb7bfd000 s>) [0 s+0 S4 A32])) 2 {*movsi_internal} (nil))

(insn 6 5 7 2 ice4.c:4 (set (reg:QI 62)
        (plus:QI (subreg:QI (reg:SI 61 [ s ]) 0)
            (const_int -100 [0xffffff9c]))) 16 {addqi3}
(expr_list:REG_DEAD (reg:SI 61 [ s ])
        (nil)))

How can i prevent this ICE ?

Regards,
Shafi

[Ian Lance Taylor-3]

Mohamed Shafi <shafitvm@...> writes:

>>From ice4.c.168r.asmcons
>
> (insn 5 2 6 2 ice4.c:4 (set (reg:SI 61 [ s ])
>         (mem/c/i:SI (symbol_ref:SI ("s") [flags 0x2] <var_decl
> 0xb7bfd000 s>) [0 s+0 S4 A32])) 2 {*movsi_internal} (nil))
>
> (insn 6 5 7 2 ice4.c:4 (set (reg:QI 62)
>         (plus:QI (subreg:QI (reg:SI 61 [ s ]) 0)
>             (const_int -100 [0xffffff9c]))) 16 {addqi3}
> (expr_list:REG_DEAD (reg:SI 61 [ s ])
>         (nil)))
>
> How can i prevent this ICE ?

If asmcons is the first place that this appears, then I think it must
be coming from some asm statement.  So the first step would be to look
at the asm statement and see if it can be rewritten using a different
constraint.

Ian

[Jeff Law]

On 10/30/09 07:13, Mohamed Shafi wrote:
> Hi,
>
> I am doing a port for a 32bit target in GCC 4.4.0. The target does not
> have support for symbolic address in QImode for load operations.
You'll need to make sure to reject such addresses for QImode in
GO_IF_LEGITIMATE_ADDRESS.


>   In
> order to do this what i have done is in define_expand for moveqi
> reject symbolic address it they come in source operands and i have
> also written a predicate for *moveqi_internal to reject such cases.
>    
OK.  Nothing wrong with these steps.  Though you really need to make
sure GO_IF_LEGITIMATE_ADDRESS is defined correctly.

IRA doesn't look at operand predicates or insn conditions.  It assumes
that any insns are valid assuming any pseudo registers appearing in the
insn get suitable hard registers.

Based on the dumps you provided it appears that reg61 does not get a
hard register and reload is generating the problematical insn #24.  This
is a good indication that your GO_IF_LEGITIMATE_ADDRESS is incorrectly
implemented.


jeff

[Mohamed Shafi]

2009/10/30 Jeff Law <law@...>:

> On 10/30/09 07:13, Mohamed Shafi wrote:
>>
>> Hi,
>>
>> I am doing a port for a 32bit target in GCC 4.4.0. The target does not
>> have support for symbolic address in QImode for load operations.
>
> You'll need to make sure to reject such addresses for QImode in
> GO_IF_LEGITIMATE_ADDRESS.
>
>
>>  In
>> order to do this what i have done is in define_expand for moveqi
>> reject symbolic address it they come in source operands and i have
>> also written a predicate for *moveqi_internal to reject such cases.
>>
>
> OK.  Nothing wrong with these steps.  Though you really need to make sure
> GO_IF_LEGITIMATE_ADDRESS is defined correctly.
>
> IRA doesn't look at operand predicates or insn conditions.  It assumes that
> any insns are valid assuming any pseudo registers appearing in the insn get
> suitable hard registers.
>
> Based on the dumps you provided it appears that reg61 does not get a hard
> register and reload is generating the problematical insn #24.  This is a
> good indication that your GO_IF_LEGITIMATE_ADDRESS is incorrectly
> implemented.
>

   I the GO_IF_LEGITIMATE_ADDRESS address macro i am allowing this
address because the target supports symbolic address in QImode for
store operations. And in the macro GO_IF_LEGITIMATE_ADDRESS there is
no option to check if the address is used in load or store. Thats why
in define_expand for moveqi i reject symbolic address it they come in
source operands and a predicate for *moveqi_internal to reject such
cases. But still i am getting the ICE.  IIRC the control does not come
to TARGET_SECONDARY_RELOAD also. How can i overcome this?

Regards,
Shafi

[Mohamed Shafi]

2009/10/30 Ian Lance Taylor <iant@...>:

> Mohamed Shafi <shafitvm@...> writes:
>
>>>From ice4.c.168r.asmcons
>>
>> (insn 5 2 6 2 ice4.c:4 (set (reg:SI 61 [ s ])
>>         (mem/c/i:SI (symbol_ref:SI ("s") [flags 0x2] <var_decl
>> 0xb7bfd000 s>) [0 s+0 S4 A32])) 2 {*movsi_internal} (nil))
>>
>> (insn 6 5 7 2 ice4.c:4 (set (reg:QI 62)
>>         (plus:QI (subreg:QI (reg:SI 61 [ s ]) 0)
>>             (const_int -100 [0xffffff9c]))) 16 {addqi3}
>> (expr_list:REG_DEAD (reg:SI 61 [ s ])
>>         (nil)))
>>
>> How can i prevent this ICE ?
>
> If asmcons is the first place that this appears, then I think it must
> be coming from some asm statement.  So the first step would be to look
> at the asm statement and see if it can be rewritten using a different
> constraint.
>

   No this appears from the rtl expand onwards.

Shafi

[Jeff Law]

>     I the GO_IF_LEGITIMATE_ADDRESS address macro i am allowing this
> address because the target supports symbolic address in QImode for
> store operations.
If your target can not use a symbolic address in a QImode load, then
GO_IF_LEGITIMATE_ADDRESS must reject symbolic addresses in QImode.  It's
that simple.

jeff