Lattice Mico32 port

[David Edelsohn-2]

        I am pleased to announce that the GCC Steering Committee has
accepted the Lattice Mico32 port for inclusion in GCC.  The initial
patch needs approval from a GCC GWP maintainer before it may be committed.

Happy hacking!
David

[Jon Beniston-3]

> I am pleased to announce that the GCC Steering Committee has
> accepted the Lattice Mico32 port for inclusion in GCC.  The initial
> patch needs approval from a GCC GWP maintainer before it
> may be committed.

Great - thanks.

Probably best to review an updated patch which is attached, which implements
all the 4.5 changes.

Cheers,
Jon

ChangeLog

gcc/
2009-09-21  Jon Beniston <jon@...>

        * config.gcc: Add lm32 elf and linux targets.
        * config/lm32: New directory.
        * config/lm32/arithmetic.c: New file.
        * config/lm32/crti.S: New file.
        * config/lm32/crtn.S: New file.
        * config/lm32/lib1funcs.S: New file.
        * config/lm32/lm32.c: New file.
        * config/lm32/lm32.h: New file.
        * config/lm32/lm32.md: New file.
        * config/lm32/lm32.opt: New file.
        * config/lm32/lm32-protos.h: New file.
        * config/lm32/predicates.md: New file.
        * config/lm32/t-elf: New file.
        * config/lm32/t-linux: New file.
        * config/lm32/t-lm32: New file.
        * config/lm32/uclinux-elf.h: New file.
        * config/lm32/xm-lm32.h: New file.


gcc/testsuite/
2009-09-21  Jon Beniston <jon@...>

        * lib/target-supports.exp (check_profiling_available): lm32 target
          doesn't support profiling.
        * gcc.dg/builtins-config.h: lm32 doesn't have the entire C99
runtime.
        * gcc.dg/20020312-2.c: Add lm32 support.
        * g++.dg/other/packed1.C: Expect to fail on lm32.        
        * g++.old-deja/g++.jason/thunk3.C: Likewise.                

libgcc/
2009-09-21  Jon Beniston <jon@...>

        * config.host: Add lm32 targets.

[Joseph S. Myers]

On Mon, 21 Sep 2009, Jon Beniston wrote:

> Probably best to review an updated patch which is attached, which implements
> all the 4.5 changes.

The target-side files now need to use the new GPLv3 exception, not the old
GPLv3 one.

>         * config/lm32/xm-lm32.h: New file.

As I said before, this file is not needed.  It looks like you've removed
it; you need to update the ChangeLog entries.

>         * gcc.dg/builtins-config.h: lm32 doesn't have the entire C99
> runtime.

Likewise.

> +/* Abort after printing out a specific insn.  */
> +static void
> +abort_with_insn (rtx insn, const char *reason)
> +{
> +  error (reason);
> +  debug_rtx (insn);
> +  abort ();
> +}

Use the GCC-standard fatal_insn instead of inventing your own
error-reporting functions (if you invent your own you need to take care
about i18n, which you didn't here).

There are several abort () calls elsewhere in the back end that should use
gcc_unreachable () (or maybe gcc_assert in some cases).

I have not checked whether my previous comments are addressed.

--
Joseph S. Myers
joseph@...

[Jon Beniston-3]

> The target-side files now need to use the new GPLv3 exception,
> not the old GPLv3 one.

Done.

>>         * config/lm32/xm-lm32.h: New file.
>
> As I said before, this file is not needed.  
> It looks like you've removed it; you need to update the ChangeLog entries.

Yep. Sorry.

> Use the GCC-standard fatal_insn instead of inventing your own
> error-reporting functions

Done.

> There are several abort () calls elsewhere in the back end

Done.

> I have not checked whether my previous comments are addressed.

Hopefully I should have addressed them already.

New patch attached. Thanks again for the feedback.

Cheers,
Jon

ChangeLog

gcc/
2009-09-22  Jon Beniston <jon@...>

        * config.gcc: Add lm32 elf and uclinux targets.
        * config/lm32: New directory.
        * config/lm32/arithmetic.c: New file.
        * config/lm32/crti.S: New file.
        * config/lm32/crtn.S: New file.
        * config/lm32/lib1funcs.S: New file.
        * config/lm32/lm32.c: New file.
        * config/lm32/lm32.h: New file.
        * config/lm32/lm32.md: New file.
        * config/lm32/lm32.opt: New file.
        * config/lm32/lm32-protos.h: New file.
        * config/lm32/predicates.md: New file.
        * config/lm32/sfp-machine.h: New file.
        * config/lm32/t-fprules-softfp: New file.
        * config/lm32/t-lm32: New file.
        * config/lm32/uclinux-elf.h: New file.
        * doc/invoke.texi: Document lm32 options.
        * doc/contrib.texi: Document lm32 porter.
        * doc/install.texi: Document lm32 targets.

gcc/testsuite/
2009-09-22  Jon Beniston <jon@...>

        * lib/target-supports.exp (check_profiling_available): lm32 target
          doesn't support profiling.
        * gcc.dg/20020312-2.c: Add lm32 support.
        * g++.dg/other/packed1.C: Expect to fail on lm32.        
        * g++.old-deja/g++.jason/thunk3.C: Likewise.                

libgcc/
2009-09-22  Jon Beniston <jon@...>

        * config.host: Add lm32 targets.
        * config/lm32: New directory.
        * config/lm32/t-elf: New file.
        * config/lm32/t-uclinux: New file.

[Richard Henderson-2]

> +#define PSEUDO_REG_P(X) ((X)>=FIRST_PSEUDO_REGISTER)

There's already a HARD_REGISTER_NUM_P that's the exact inverse.

> +#define G_REG_P(X)      ((X)<32)

I suppose you're planning to add floating point registers?

> +#define CONST_OK_FOR_LETTER_P(VALUE, C)                 \
> +(  (C) == 'J' ? (VALUE) == 0                            \
> + : (C) == 'K' ? MEDIUM_INT (VALUE)                      \
> + : (C) == 'L' ? MEDIUM_UINT (VALUE)                     \
> + : (C) == 'M' ? LARGE_INT (VALUE)                       \
> + : 0                                                    \
> +)
> +
> +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  0

These defines are replaced by define_constraint,
typically in constraints.md.

> +/* FIXME - This is not yet supported.  */
> +#define STATIC_CHAIN_REGNUM 3

While you don't actually support this yet, you'd do well to
define it to one of the call-clobbered registers that isn't
an argument register -- r9 or r10 by the looks of it.

> +#define GO_IF_LEGITIMATE_ADDRESS(m,x,l)                 \

Use the TARGET_LEGITIMATE_ADDRESS_P target hook.

> +#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)          \

Copy and paste?

> +#define MEDIUM_INT(X)  ((((HOST_WIDE_INT)(X)) >= -32768) && (((HOST_WIDE_INT)(X)) < 32768))
> +#define MEDIUM_UINT(X) (((unsigned HOST_WIDE_INT)(X)) < 65536)

Use the IN_RANGE macro.  And if you move these to define_constraints, as
mentioned above, you won't need the cast to HOST_WIDE_INT.

 > +#define LARGE_INT(X)                                    \
 > +((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1)               \
 > + && (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)

Did you really want a signed low and an unsigned high on this?  It would
seem that at some point you're getting signed and unsigned values
confused somewhere if you need this...

> +__ashlsi3:
> +        /* Only use 5 LSBs, as that's all the h/w shifter uses.  */
> +        andi    r2, r2, 0x1f
> +        /* Get address of offset into unrolled shift loop to jump to.  */
> +#ifdef __PIC__
> +        orhi    r3, r0, gotoffhi16(__ashlsi3_table)
> +        addi    r3, r3, gotofflo16(__ashlsi3_table)
> +        add     r3, r3, gp
> +#else
> +        mvhi    r3, hi(__ashlsi3_table)
> +        ori     r3, r3, lo(__ashlsi3_table)
> +#endif

Seems like avoiding the table and knowing that each entry is 4 bytes
back would be a teeny bit faster.

        mvhi r3, hi(__ashlsi3_0)
        add r2, r2, r2
        ori r3, r3, lo(__ashlsi3_0)
        add r2, r2, r2
        sub r3, r3, r2
        b r3

Also, it would seem that you'd be able to arrange for these alternate
entry points to be invoked directly.  Something like

(define_insn "*ashlsi3_const"
   [(set (match_operand:SI 0 "register_operand" "=R1")
         (ashift:SI (match_operand:SI 1 "register_operand" "0")
                    (match_operand:SI 2 "const_5bit_operand" "i")))
    (clobber (match_scratch:SI 3 "=RA"))]
   "!TARGET_BARREL_SHIFT_ENABLED"
   "calli __ashlsi3_%2"
   [(set_attr "type" "call")])

Where R1 and RA are singleton register classes for those respective
registers.  Obviously you can delay this as an improvement for later.

> +      /* Raise divide by zero exception.  */
> +      int eba;
> +      __asm__ __volatile__ ("rcsr %0, EBA":"=r" (eba));
> +      eba += 32 * 5;
> +      __asm__ __volatile__ ("mv ea, ra");
> +      __asm__ __volatile__ ("b %0"::"r" (eba));

You want to put __builtin_unreachable() there after the branch.

> +          emit_insn (gen_movsi_imm_lo (operands[0], operands[0], GEN_INT (INTVAL (operands[1]))));

Line wrap.  There are other instances too.

> +(define_insn "movsi_kimm"
> +(define_insn "movsi_limm"
> +(define_insn "movsi_imm_hi"
> +(define_insn "movsi_reloc_gprel"
> +(define_insn "movsi_reloc_hi"
> +(define_insn "*movsi_insn"

Having these as separate instruction patterns is an extremely bad idea.
  All moves of a given mode should be in the same pattern, so that
reload can have the freedom to do its spilling as needed.  While your
unspecs are except from this, things that just use HIGH aren't.

Using HIGH and LO_SUM on integer constants is a bad idea.  Much better
to just go ahead and create a constraint letter; see for instance
Alpha's define_constraint "L".

> +(define_insn "*movqi_insn"
> +  [(set (match_operand:QI 0 "register_or_memory_operand" "=r,r,m")
> +        (match_operand:QI 1 "register_or_memory_operand" "m,r,r"))]

Not having QImode or HImode constants is a mistake.

> +static bool
> +lm32_frame_pointer_required (void)
> +{
> +  /* If the function contains dynamic stack allocations, we need to
> +     use the frame pointer to access the static parts of the frame.  */
> +  if (cfun->calls_alloca)
> +    return true;

alloca is handled for you by generic code.
You shouldn't need to define this hook at all.



r~

[Jon Beniston-3]

Thanks for the feedback Richard. The attached patch should address pretty
much everything you have mentioned, except for adding this:

(define_insn "*ashlsi3_const"
   [(set (match_operand:SI 0 "register_operand" "=R1")
         (ashift:SI (match_operand:SI 1 "register_operand" "0")
                    (match_operand:SI 2 "const_5bit_operand" "i")))
    (clobber (match_scratch:SI 3 "=RA"))]
   "!TARGET_BARREL_SHIFT_ENABLED"
   "calli __ashlsi3_%2"
   [(set_attr "type" "call")])


As I kept on getting "unable to find a register to spill in class R1" and
wasn't sure how to fix it. As you say, this is something that can be added
later. I've also fixed a few other issues that have cropped up during
testing.

Cheers,
Jon

ChangeLog

gcc/
2009-09-28  Jon Beniston <jon@...>

        * config.gcc: Add lm32 elf and uclinux targets.
        * config/lm32: New directory.
        * config/lm32/arithmetic.c: New file.
        * config/lm32/crti.S: New file.
        * config/lm32/crtn.S: New file.
        * config/lm32/lib1funcs.S: New file.
        * config/lm32/lm32.c: New file.
        * config/lm32/lm32.h: New file.
        * config/lm32/lm32.md: New file.
        * config/lm32/lm32.opt: New file.
        * config/lm32/lm32-protos.h: New file.
        * config/lm32/predicates.md: New file.
        * config/lm32/sfp-machine.h: New file.
        * config/lm32/t-fprules-softfp: New file.
        * config/lm32/t-lm32: New file.
        * config/lm32/uclinux-elf.h: New file.
        * doc/invoke.texi: Document lm32 options.
        * doc/contrib.texi: Document lm32 porter.
        * doc/install.texi: Document lm32 targets.

gcc/testsuite/
2009-09-28  Jon Beniston <jon@...>

        * lib/target-supports.exp (check_profiling_available): lm32 target
          doesn't support profiling.
        * gcc.dg/20020312-2.c: Add lm32 support.
        * g++.dg/other/packed1.C: Expect to fail on lm32.        
        * g++.old-deja/g++.jason/thunk3.C: Likewise.                

libgcc/
2009-09-28  Jon Beniston <jon@...>

        * config.host: Add lm32 targets.
        * config/lm32: New directory.
        * config/lm32/t-elf: New file.
        * config/lm32/t-uclinux: New file.

[Richard Henderson-2]

> +(define_predicate "no_pic_small_symbol"
> +  (match_code "symbol_ref")
> +{
> +  return !flag_pic & SYMBOL_REF_SMALL_P (op);
> +})

s/&/&&/

> Index: gcc/config/lm32/sfp-machine.h
> Index: gcc/config/lm32/crti.S
> Index: gcc/config/lm32/lib1funcs.S
> Index: gcc/config/lm32/crtn.S
> Index: gcc/config/lm32/arithmetic.c
> Index: gcc/config/lm32/t-fprules-softfp
> Index: gcc/config/lm32/t-lm32

Can you move these to libgcc?

> +#define CPP_SPEC "\
> +%{mmultiply-enabled:-D__multiply_enabled__} \
> +%{mdivide-enabled:-D__divide_enabled__} \
> +%{mbarrel-shift-enabled:-D__barrel_shift_enabled__} \
> +%{msign-extend-enabled:-D__sign_extend_enabled__} \
> +%{muser-enabled:-D__user_enabled__} \

It would be nicer to merge this into TARGET_CPU_CPP_BUILTINS.

You forgot to include constraints.md in your patch.

> +(define_insn "*movqi_insn"
> +  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r")
> +        (match_operand:QI 1 "general_operand" "m,r,r,K,L"))]
> +  ""
> +  "@
> +   lbu      %0, %1
> +   or       %0, %1, r0
> +   sb       %0, %1
> +   addi     %0, r0, %1
> +   ori      %0, r0, %1"
> +  [(set_attr "type" "load,arith,store,arith,arith")]

You don't need both addi and ori alternatives, since all legal QImode
constants can be handled by addi.  You can use the 'n' constraint here.

> +  if (GET_CODE (operands[1]) == CONST_INT)
> +    {
> +      operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
> +      emit_insn (gen_movsi (operands[0], operands[1]));
> +      DONE;
> +    }

These bits aren't needed in the QI and HImode expanders.

Generally ports have an extra constraint to prevent MEM-to-MEM moves
from being generated by combine.  You prevent them from happening in
initial rtl generation in your expanders, but you should probably have
something like

bool l32m_move_ok (enum machine_mode mode, rtx operands[2])
{
   if (memory_operand (mode, operands[0]))
     return register_or_zero_operand (mode, operands[1]);
   return true;
}

Oh, that reminds me.  I don't see a move alternative that allows R0
as the RHS of a store.

> +(define_split
> +  [(set (match_operand:SI 0 "register_operand" "")
> +        (match_operand:SI 1 "reloc_operand" ""))]
> +  "!flag_pic"
> +  [(set (match_dup 0) (high:SI (match_dup 1)))
> +   (set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
> +  ""
> +)

Why do you need this?  Are you finding some pass putting these
symbols back together again?  If so, you've missed making these
symbols not be legitimate constants.  Yep:

> +#define LEGITIMATE_CONSTANT_P(X) 1

that's exactly your problem.

> +(define_insn "*movsi_lo_sum"
> +  [(set (match_operand:SI 0 "register_operand" "=r")
> +        (lo_sum:SI (match_operand:SI 1 "register_operand" "0")
> +                   (match_operand:SI 2 "reloc_operand" "i")))]
> +  "!flag_pic"
> +  "ori      %0, %0, lo(%2)"
> +  [(set_attr "type" "arith")]

Is this really an unsigned relocation?  I strongly suggest that
you make the hi/lo relocation pair use a signed low-part.  This
allows you to merge the lo_sum into a memory:

        // foo++;
        orhi r1, r0, hi(foo)
        ori r1, r1, lo(foo)
        lw r2, (r1+0)
        addi r2, r2, 1
        sw r2, (r1+0)
=>
        orhi r1, r0, hi(foo)
        lw r2, (r1+lo(foo))
        addi r2, r2, 1
        sw r2, (r1+lo(foo))

        // x = foo[n]
        orhi r1, r0, hi(foo)
        ori r1, r1, lo(foo)
        add r1, r1, r2
        lw r3, (r1+0)
=>
        orhi r1, r0, hi(foo)
        add r1, r1, r2
        lw r3, (r1+lo(foo))

FWIW, powerpc provides both signed and unsigned variants of
its hi relocation; "@ha" is supposed to mean "high for add"
or somesuch.

All that said, fixing this is not a requirement.

> +(define_expand "indirect_jump"
> +  [(set (pc) (match_operand 0 "register_operand" ""))]
> +  ""
> +  "
> +{
> +  emit_jump_insn (gen_indirect_jumpsi (operands[0]));
> +  DONE;
> +}")
> +
> +(define_insn "indirect_jumpsi"
> +  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
> +  ""
> +  "b        %0"
> +  [(set_attr "type" "uibranch")]
> +)

You can eliminate the expander and just use the insn.

> +(define_expand "call"
> +  [(parallel [(call (match_operand 0 "memory_operand" "m")
> +                    (match_operand 1 "" ""))
> +              (clobber (reg:SI RA_REGNUM))
> +             ])]
> +  ""
> +  "
> +{
> +  rtx addr = XEXP (operands[0], 0);
> +  if (!CONSTANT_ADDRESS_P (addr))
> +    {
> +      emit_call_insn (gen_call_via_regsi (addr, operands[1]));
> +      DONE;
> +    }
> +}")

(define_expand "call"
   [(parallel [(call (match_operand 0 "" "")
                    (match_operand 1 "" ""))
              (clobber (reg:SI RA_REGNUM))])]
   ""
{
   rtx addr = XEXP (operands[0], 0);
   if (!CONSTANT_ADDRESS_P (addr))
     XEXP (operands[0], 0) = force_reg (Pmode, addr);
})

(define_insn "*call"
   [(call (mem (match_operand:SI 0 "call_operand" "r,s"))
          (match_operand 1 "" ""))
    (clobber (reg:SI RA_REGNUM))]
   ""
   "@
    call %0
    calli %0"
   [(set_attr "type" "call")])

(1) Don't use "memory_operand" for the call.  The things you
     are being passed aren't validized memories, the predicate
     is never invoked, and it's a teeny bit confusing.

(2) No reason not to merge the register and symbolic insns.

(3) Similar for call_value, of course.

> +(define_insn "addsi3"
> +  [(set (match_operand:SI 0 "register_operand" "=r,r")
> +        (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ,rJ")
> +                 (match_operand:SI 2 "register_or_K_operand" "r,K")))]

You ought to use "%" for all of the commutative patterns for
which the two operands don't have identical constraints.  I.e.
yes here on the add, but not on the beq pattern since those two
operands are both register_or_zero_operand.

Lots of nit picks, but your port is actually looking very good.


r~

[Richard Henderson-2]

On 09/28/2009 03:51 PM, Jon Beniston wrote:

> (define_insn "*ashlsi3_const"
>     [(set (match_operand:SI 0 "register_operand" "=R1")
>           (ashift:SI (match_operand:SI 1 "register_operand" "0")
>                      (match_operand:SI 2 "const_5bit_operand" "i")))
>      (clobber (match_scratch:SI 3 "=RA"))]
>     "!TARGET_BARREL_SHIFT_ENABLED"
>     "calli __ashlsi3_%2"
>     [(set_attr "type" "call")])
>
> As I kept on getting "unable to find a register to spill in class R1" and
> wasn't sure how to fix it. As you say, this is something that can be added
> later. I've also fixed a few other issues that have cropped up during
> testing.

We can have a look at this again once your port is committed.

Worse come to worse, we could add more such functions which operate on
more registers (perhaps 4?).  E.g.  __ashlsi3_R_N where R is the
register number to operate on, and N is the number of bits to shift.
Then you'd need to measure to see what kind of size vs speed impact this
has for the kind of applications you are targeting.

Oh, we'd probably have to be sure to make all of these functions hidden,
so that you don't wind up going through the dynamic linker.


r~

[Jon Beniston-3]

Hi Richard,

>> Index: gcc/config/lm32/sfp-machine.h
>> Index: gcc/config/lm32/crti.S
>> Index: gcc/config/lm32/lib1funcs.S
>> Index: gcc/config/lm32/crtn.S
>> Index: gcc/config/lm32/arithmetic.c
>> Index: gcc/config/lm32/t-fprules-softfp
>> Index: gcc/config/lm32/t-lm32
>
>Can you move these to libgcc?

The rules in libgcc/Makefile.in use $(gcc_srcdir) (E.g. for targets
lib1asmfuncs-o). How would you suggest I do this?

Cheers,
Jon

[Ian Lance Taylor-3]

"Jon Beniston" <jon@...> writes:

> Hi Richard,
>
>>> Index: gcc/config/lm32/sfp-machine.h
>>> Index: gcc/config/lm32/crti.S
>>> Index: gcc/config/lm32/lib1funcs.S
>>> Index: gcc/config/lm32/crtn.S
>>> Index: gcc/config/lm32/arithmetic.c
>>> Index: gcc/config/lm32/t-fprules-softfp
>>> Index: gcc/config/lm32/t-lm32
>>
>>Can you move these to libgcc?
>
> The rules in libgcc/Makefile.in use $(gcc_srcdir) (E.g. for targets
> lib1asmfuncs-o). How would you suggest I do this?

You can put assembler files in LIB2ADD.  See, e.g.,
libgcc/config/ia64/t-softfp-compat.  I'm not sure the libgcc1
vs. libgcc2 distinction makes much sense any more.

Ian

[Jon Beniston-3]

Hi,

Attached is an updated LM32 patch that hopefully addresses Richard's last
comments, with the following exceptions.

>> Index: gcc/config/lm32/sfp-machine.h
>> Index: gcc/config/lm32/crti.S
>> Index: gcc/config/lm32/lib1funcs.S
>> Index: gcc/config/lm32/crtn.S
>> Index: gcc/config/lm32/arithmetic.c
>> Index: gcc/config/lm32/t-fprules-softfp
>> Index: gcc/config/lm32/t-lm32
>
>Can you move these to libgcc?

I've moved all of these except for the softfp files, as I'm not sure how
that should be made to work.

> I strongly suggest that
> you make the hi/lo relocation pair use a signed low-part.
> All that said, fixing this is not a requirement.

That's a good suggestion, thanks, but I'd like to add that later, if that's
ok.

Cheers,
Jon

ChangeLog

gcc/
2009-10-06  Jon Beniston <jon@...>

        * config.gcc: Add lm32 elf and uclinux targets.
        * config/lm32: New directory.
        * config/lm32/lm32.c: New file.
        * config/lm32/lm32.h: New file.
        * config/lm32/lm32.md: New file.
        * config/lm32/lm32.opt: New file.
        * config/lm32/lm32-protos.h: New file.
        * config/lm32/constraints.md: New file.
        * config/lm32/predicates.md: New file.
        * config/lm32/sfp-machine.h: New file.
        * config/lm32/t-fprules-softfp: New file.
        * config/lm32/uclinux-elf.h: New file.
        * doc/invoke.texi: Document lm32 options.
        * doc/contrib.texi: Document lm32 porter.
        * doc/install.texi: Document lm32 targets.

gcc/testsuite/
2009-10-06  Jon Beniston <jon@...>

        * lib/target-supports.exp (check_profiling_available): lm32 target
          doesn't support profiling.
        * gcc.dg/20020312-2.c: Add lm32 support.
        * g++.dg/other/packed1.C: Expect to fail on lm32.        
        * g++.old-deja/g++.jason/thunk3.C: Likewise.                

libgcc/
2009-10-06  Jon Beniston <jon@...>

        * config.host: Add lm32 targets.
        * config/lm32: New directory.
        * config/lm32/libgcc_lm32.h: New file.
        * config/lm32/_mulsi3.c: New file.
        * config/lm32/_udivmodsi4.c: New file.
        * config/lm32/_divsi3.c: New file.
        * config/lm32/_modsi3.c: New file.
        * config/lm32/_udivsi3.c: New file.
        * config/lm32/_umodsi3.c: New file.
        * config/lm32/_lshrsi3.S: New file.
        * config/lm32/_ashrsi3.S: New file.
        * config/lm32/_ashlsi3.S: New file.
        * config/lm32/crti.S: New file.
        * config/lm32/crtn.S: New file.
        * config/lm32/t-lm32: New file.
        * config/lm32/t-elf: New file.
        * config/lm32/t-uclinux: New file.

[Richard Henderson-2]

The port is ok to check in.


r~

[Jon Beniston-3]

> The port is ok to check in.

Great - so can I apply it, or does someone else need to?

Cheers,
Jon

[David Edelsohn-3]

On Wed, Oct 21, 2009 at 7:49 AM, Jon Beniston <jon@...> wrote:
>> The port is ok to check in.
>
> Great - so can I apply it, or does someone else need to?

Until you have write access to the repository, someone else needs to
commit the patch for you.

The GCC community generally likes to see a few examples of patches
(correctness, coding standards) and knowledge about version control
repositories before giving write access.

Thanks, David

[Sébastien Bourdeauducq]

Hi,

On Tuesday 03 November 2009 17:52:40 David Edelsohn wrote:
> On Wed, Oct 21, 2009 at 7:49 AM, Jon Beniston <jon@...> wrote:
> >> The port is ok to check in.
> >
> > Great - so can I apply it, or does someone else need to?
>
> Until you have write access to the repository, someone else needs to
> commit the patch for you.

Has somebody been assigned to committing this patch?

Thanks,
Sébastien