MCP55 SATA solution to test

[Alexander Motin-3]

Hi.

Thanks to one man who provided access to his machine, I seem to found
how to fix device detection on nVidia MCP55 SATA controller on amd64
8.0. Looks like this controller need some time (very short) to enable
BAR(5) memory access after PCI configuration register written. Probably
some changes in PCI code exposed this issue. Also it explains why
setting hw.pci.mcfg to 0 helps.

Attached patch solves problem for that machine. Testers are welcome.

--
Alexander Motin

--- ata-nvidia.c.prev 2009-10-25 03:13:57.000000000 +0300
+++ ata-nvidia.c 2009-10-25 03:15:52.000000000 +0300
@@ -165,7 +165,8 @@ ata_nvidia_chipinit(device_t dev)
 
     /* enable control access */
     pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) | 0x04,1);
-
+    /* MCP55 seems to need some time to allow r_res2 read. */
+    DELAY(10);
     if (ctlr->chip->cfg1 & NVQ) {
  /* clear interrupt status */
  ATA_OUTL(ctlr->r_res2, offset, 0x00ff00ff);

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[Rainer Hurling]

On 25.10.2009 02:46 (UTC+2), Alexander Motin wrote:

> Hi.
>
> Thanks to one man who provided access to his machine, I seem to found
> how to fix device detection on nVidia MCP55 SATA controller on amd64
> 8.0. Looks like this controller need some time (very short) to enable
> BAR(5) memory access after PCI configuration register written. Probably
> some changes in PCI code exposed this issue. Also it explains why
> setting hw.pci.mcfg to 0 helps.
>
> Attached patch solves problem for that machine. Testers are welcome.
>
>
>
> ------------------------------------------------------------------------

I tried your patch on my 'MSI K9N Neo' with MCP55 SATA controller on
todays 9.0-CURRENT (amd64) and it works!

A delay of 10 microseconds after hours and days of looking for a reason
of this failure. That's really funny ...

Many many thanks for your solution. Please submit it,
Rainer

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[Marco Broeder]

On Sun October 25 2009 02:46:57 Alexander Motin wrote:

> Hi.
>
> Thanks to one man who provided access to his machine, I seem to found
> how to fix device detection on nVidia MCP55 SATA controller on amd64
> 8.0. Looks like this controller need some time (very short) to enable
> BAR(5) memory access after PCI configuration register written. Probably
> some changes in PCI code exposed this issue. Also it explains why
> setting hw.pci.mcfg to 0 helps.
>
> Attached patch solves problem for that machine. Testers are welcome.
>

Success! I tested your patch and everything is working fine
with hw.pci.mcfg set to 1, now. Please commit it.

Many thanks!

--
Regards,
Marco Bröder <marco.broeder@...>
OpenPGP key fingerprint: 5615 106E 031A F3D3 64CC 0F9E 4DCE 6524 F595 082F
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[Pascal Hofstee]

2009/10/25 Alexander Motin <mav@...>:

> Hi.
>
> Thanks to one man who provided access to his machine, I seem to found
> how to fix device detection on nVidia MCP55 SATA controller on amd64
> 8.0. Looks like this controller need some time (very short) to enable
> BAR(5) memory access after PCI configuration register written. Probably
> some changes in PCI code exposed this issue. Also it explains why
> setting hw.pci.mcfg to 0 helps.
>
> Attached patch solves problem for that machine. Testers are welcome.

Confirmed this also fixes the SATA detection on my MSI K9N Neo on 9.0-CURRENT.
Please commit :)
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