MPC555 HARDWARE DESIGN CHECKLIST

[fivefifteensystems]

Has anyone seen an update to this checklist?

Dan

MPC555 HARDWARE DESIGN CHECKLIST
The following HARDWARE CHECKLIST for designing with the MPC555.
By Thomas Walter  8/28/2000

Please send feedback/questions/comments to:  
thomas.walter@...

Sincerely,  Thomas Walter


This document will cover the MPC555, in the most common application
of a single microcontroller with external bus devices.

You MUST read the MPC555 User's Manual to insure you have all the
pins assigned correctly. This document is to help you avoid common
errors, but can not foresee every possible application.

HISTORY:
--------
Revision 0.86 -- 28 August 2000 Thomas Walter
     CORRECTION - JTAG TRST* connects to PORESET*

Revision 0.85 -- 22 May 2000  Thomas Walter
     updated Vddsyn filter.              

Revision 0.84 -- 28 April 2000   Thomas Walter

BACKGROUND
----------

Overview of common connections for the MPC555 schematics.

Which pins should have pull up or pull down resistors?

RESET
-----

PORESET PIN:
· Initializes everything, also used to sync the PLL.
· Generally used as a reset input when power is lost to the
module.
· Initializes timer registers, which was not true on the MPC509.
· Recommendation:  Use as a CPU reset input after losing keep
alive 3.3V and switched power, or at first connecting the battery.  
Use a diode and pullup to 3.3V to prevent shutting down car if keep
alive power is lost without losing switched power.
· The MPC555 asserts internal PORESET if it detects keep alive
voltage dropping below a threshold.
· Generally only used when the vehicle battery is reconnected.
· PORESET does not guarantee Data Coherency.
· PORESET needs to remains low long enough for the PLL to lock
(i.e. KAPWR 3.3V to come up to voltage) prior to PORESET
deasserting.  PORESET must be driven by an external source, do not
leave floating.

HRESET PIN:
· Pull up to 3.3V with a 10K pull up resistor
· Initializes registers other than those kept alive by keep
alive power.
· Generally used as a key-on (automotive application) reset
input.
· Used by SDS/Macraigor tools to reset the processor via the
BDM connector.
· Use as a CPU reset input from the power supply.

SRESET PIN:
· Pull up to 3.3V with a 10K pull up resistor
· Recommendation: Use as a CPU output to memory and/or
peripherals reset  input pin.
· All 3  reset inputs (PORESET, HRESET, SRESET) will not
recognize active pulses below 20ns.  Minimum time to guarantee reset
input is recognized is 100 ns.
· For additional information, see chapters 7 & 8 of the MPC555
Users Manual.


RESET CONFIGURATION WORD
-------------------------

RSTCONF:  (Reset Configuration Word) see  7.5 Reset Configuration
chapter 7 of MPC555 User's Manual.
· There are three options to use configuration words:
1. internal flash  - Pull up through a 10K resistor to 3.3V note
flash configuration bit HC is programmed to 0  (CMFCFIG register -
bit HC is programmed to 0) reset configuration is read from the
internal flash shadow array.
2. external word - Pull down through a 10K resistor to ground
reset configuration word is read from the Data Bus
3. default (cannot boot from internal flash) - Pull up through a
10K resistor to 3.3V note flash configuration bit HC is set to 1  
(CMFCFIG register - bit HC is not programmed)  reset configuration
word is set to 0x0000 0000
· If TEXP Feature is needed in a system, then connect RSTCONF
to SRESET to use TEXP Functionality.

NOTE:  REV G ISSUE: [Fixed in Rev K and later]: Data bits 13 & 14 of
the Reset Configuration Word will control the External Bus Division
Factor [EBDF]. It has been note on rev G that they seem susceptible
to this external bit over-riding the internal reset config word.  
[Bit 13 is listed as reserve, but was a divide by four in the
original specification, but this is subject to change in future
revisions]

-----

EXTCLK  (EXTERNAL CLOCK INPUT):
· If this input will not be used, it must be connected directly
to ground. For a prototype board, a pull down resistor could be used,
allowing an external clock to be used during development. For
production the pin should be grounded to prevent EMI from disturbing
the MPC555 clock circuitry.


ENGCLK/BUCLK:  Engineering Clock Output / Backup Clock Output
· Output of the engineering clock.
· This a different pin and function than ECK, discussed later.
· Pull down with a 10K resistor to ground to reduce EMI.  This
is also helpful during debugging to check is the clock is running in
Limp mode  (approximately 7 Mhz).

XTAL/EXAL:
4Mhz or 20Mhz XTAL.  Recommendation is to use the 4Mhz.  Less EMI
emissions from the oscillator.

XFC:
· put a capacitor between XFC and VDDSYN
· For a 4MHz XTAL, MF+1 = 10: the equation in section 8.3.5 of
the MPC555 Users manual gives a result of 11 nfd, use a 10 nfd (40Mhz
operation)
· Calculate the value of XFC for the normal operating frequency.
· The value of the XFC capacitor can be varied. By using a
capacitor that is larger in size (i.e. 5X) , will result in a more
stable clock, however time to lock will take longer. Since each board
layout is different, you would have to look at your own system to
look at the tradeoffs.
· This pin is extremely sensitive. Place the capacitor as XFC
capacitor as close as possible, keep line lengths as short as
possible, and avoid routing signals next to this pin.

NOTE:  REV G & REV K ONLY [FIXED IN K2 and later]:  We have noted
problems at startup on these devices. In some cases two resistors as
a voltage divide and a diode can be used to provide a voltage from
1.0 to 1.6V at this pin at powerup to assist in starting the PLL.


CLKOUT:
· If LIMP MODE is enabled, the System Clock will immediately be
driven out on the CLKOUT pin during a PORESET.
· If LIMP MODE is disabled, the System Clock will be driven out
after the PORESET is released, providing the PLL is locked.
· Additional Information is contained in the MPC555 Users
Manual. See section 7.1.1


JTAG /BDM PINS:

· JTAG/BDM pins are shared on the MPC555.  Table 6-7 in the
MPC555 Users manual outlines how the function are selected. In brief
it depends on databit 11 of the reset configuration word, debug (0)
or JTAG (1).
DSDI:  
· Use between 4K - 6.5K pull down to enable external clock on
BDM.  See Section 21.4 in the Users Manual.
DSCK:  
· Use 10K pull down to enable running in normal mode. The
debugger used must be strong enough to pull this pin HIGH to enable
debugging.
DSDO:
· output (goes to BDM connector)

FRZ/PTR:
· Use as PTR (Program Trace).  This is an output-- does not
need a resistor.

TRST PIN:
· Pull down  to prevent going into JTAG mode.

NOTE:  If JTAG is being used on the device, DO NOT hardwire PORESET
to TRST, but use a 1K resistor in series as the pins can both act as
output at times.

TMS PIN:
· Pull up to 3.3V  (to Prevent Entering JTAG Mode)

RECOMMENDATION: INSTALL A 10 PIN BDM CONNECTION:
NOTE THERE ARE THREE POSSIBLE BDM Options. The connections to pins 1
& pin 6 will change depending on option A,B,C.

Due to various needs by different customers, there are 3 possible pin
outs of the BDM connector. While these can be picked based on the
application, there are preferred pin outs for specific applications.
Motorola recommends that Option A be used on development systems.
Option B is the default power on reset condition.

Option A - Maximum Debug capability (access to BDM and program trace
signals):

VFLS0_MPIO32B3 (ball J18) 1   2 SRESET (ball V20)
Ground   3   4 TCK_DSCK (ball J1)
Ground   5   6 VFLS1_MPGIO32B4 (ball K18)
HRESET (ball W20) 7   8 TDI_DSDI (ball K2)
MPC  Power (3 volts) 9  10 TDO_DSDO (ball J2)

Option B - Maximum external bus capability:

IWP0/VFLS0 (ball L2) 1   2 SRESET (ball V20)
Ground   3   4 TCK_DSCK (ball J1)
Ground   5   6 IWP1/VFLS1 (ball L1)
HRESET (ball W20) 7   8 TDI_DSDI (ball K2)
MPC Power (3 volts) 9  10 TDO_DSDO (ball J2)

Option C - Maximum I/O configuration:

  SGPIO6/FRZ/PTR* (ball K3) 1   2 SRESET (ball V20)
Ground   3   4 TCK_DSCK (ball J1)
Ground   5   6 SGPIO6/FRZ/PTR* (ball K3)
HRESET (ball W20) 7   8 TDI_DSDI (ball K2)
MPC Power (3 volts) 9  10 TDO_DSDO (ball J2)


BUS ARBITRATION / WATCH POINT PINS:
1. These bus arbitration pins have alternate functions as
watchpoints.
2. For code tracing, most people want these pins used as
watchpoints.
3. Default Reset Configuration Word sets the Debug Pin
Configuration Pins (dbgc) (bits 9-10) to 00. Setting these pins to be
used as bus arbitration. See Table 6-6 and 6-8 in the User Manual.
4. Recommendation:  Set dbgc (bits 9-10 in the Reset
Configuration Word) to 11, to use these pins as watchpoints (Users
Manual 7.5.2).

INTERRUPTS:

· Use 10K pullups on pins to be programmed as IRQs.
· IRQ0 is non-maskable interrupt
· IRQ5:7 are requested be used as IRQs after reset, but are
used as MODCK[1:3] to configure the oscillator in the PLL during
PORESET.
- Confirm no external events will drive IRQ5:7 during  PORESET.

For the standard 4Mhz oscillator:  MODCK [1:3] are define as (From
table 8-1)
· IRQ5: MODCK1: pull low
· IRQ6: MODCK2: pull high
· IRQ7: MODCK3: pull low

· The MODCK pins must be stable throughout the assertion and
the rising edge of PORESET. The values are latched on rising edge of
PORESET.
· Insure hold time on MODCK pins; use delayed PORESET to enable
driver.


CS[0:3]  EXTERNAL DEVICE CHIP SELECTS.

AT[0:3]/WE[0:3]  Used as WE (Write Enables)  NOTE:  WE0* controls DATA
[0:7]
· WE1* controls DATA[8:15]
· WE2* controls DATA[16:23]
· WE3* controls DATA[24:31]

Unused MDA/PWM/GPIO/TPU
· Outputs only no resistors (PWM only except those with general
purpose inputs)
· Unused bidirectional IO pull high (less current than pulling
low) with a 10K to 5V.  If EMI is a major consideration, than pulling
the unused pins low with a 10K resistor will reduce EMI emissions. To
reduce external components configure the IO ports as outputs and set
ports to drive low.
· Inputs (digital or analog) only tie low to a common or
individual resistors. Use caution as some analog inputs can also be
digital outputs

(QADC module, for example):  
Pins pulled to Other Voltage Sources: Maximum input current is 1mA
for GPIO Pins, 3mA for QADC Pins. The total of input currents should
not exceed 10mA for the devices. (This is useful when connecting an
Input pin to a directly switched12V source. Input filtering should
still be observed)

VF[0:4]/VFLS [0:1]
· Needed by HP's logic tools for code trace as VF pins.
· These are multiplexed with other signals which can be IO.  VF
signals are multiplexed in two places.
· Note the Possible BDM options to which bring out VFLS [0:1]
· Turn off VF Pins when not needed to reduce EMI


BUS CONTROL:
· Recommendation:
1. BG*   pulled LOW. This will grant the Bus to the MPC555.[For
a single chip system, the 555 will always have the bus]
2. BR*   pulled up with 10K resistor to 3.3V
3. BB*   pulled up with 10K resistor to 3.3V
· Note resistors on BR* & BB* are not required for a single
chip system.

EPEE (External Program or Erase Enable MPC555 Users Manual section
19.7.8):
· Recommendation:  Pull high to 3.3V to allow reprogramming of
the flash.
· To prevent programming or erasing the flash:  Pull down with
a 10K resistor to ground to prevent accidental flash erase (Note Vpp
would have to be at 5V for program or erase)

VDDH:
· The 5V (Vddh) supply must lead the 3.3V (Vddl) Supply.
· An addition of a diode between the 5V and 3.3V is recommended
to insure the Vddh (5V) does not go 0.5V below the Vddl (3.3V). A
Shottky Power Rectifier (MBR052LT1 from On Semiconductor is rated at
20V 0.5V 0.385V@25C Vf  will meet this requirement).

VDDL:
· 3.3V core voltage.
· When 5V (Vddh) is applied before the 3V (Vddl) supply, all 5V
outputs will be in indeterminate states until the 3V supply reaches a
level that allows Internal Reset to be distributed throughout the
device. (Reset will propagate through the device when Vddl is greater
than 1.5V, but the core will not come out Internal Reset until Vddl
reaches specified operating voltage).

VPP:
· 5V Should only be applied to allow programming or erasing of
the internal flash.
· Rule:  3.3V core voltage must be applied prior to Vpp 5V.  
3.3V core voltage must go down after Vpp 5V.
· If Vpp is not used in circuit; Vpp should be tied to 3.3V.  
Do NOT leave pin floating, nor tied to ground.

VDDSRAM:
· Connected to keep alive (constant) power

VDDSYN:
· Filter to keep noise as low as possible. Less than 50mV &
500Hz noise. Board noise will play a major roll in what
· For a FOUR LAYER BOARD: for PLL stabilization, Use a 8.2mH
series inductor between 3.3V and VDDSYN with two pull down capacitors
from VDDSYN to ground of values 10 uf and 0.1 uf.
· For a EIGHT LAYER BOARD, typically with full analog power and
ground plane, typically you can get by with a RC filter using a 10
Ohm and 0.1ufd capacitor.

NOTE: It is recommended that before PCB layout starts, review
Appendix E of the MPC555 user's manual and give those guidelines the
highest priority. Note: In figure E-1 Option 1, is no longer needed.  
VSSSYN should be grounded.

QADC:
· ETRIG[1:2] - This is a QADC trigger Option
· Pull high for continuous scan, pull low otherwise.

NOTE:  to synchronize the TPU with the QADC, use a TPU output to
drive the QADC Etrig input.

TOUCAN PINS:
· CAN transmit and receive pins do not need resistors for the
Phillips drivers.

TPU_T2CLK:
· This external clock input is not anticipated to be used as a
TPU clock.  Use a 10K pull down

QSPI[0:6]
· Use zero ohm series resistors to protect for EMC

ECK (EXTERNAL BAUD CLOCK FOR SCI 1 & 2):
· If you do not use this external SCI clock input,  pull down
with a 10K


*** END OF FILE ***






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[Dees Randy-rsaf30]

I don't know of an update.

Note that there are errors in the below list. BG should not be pulled
low. I'd have to review the whole list again to determine if there are
any other errors. (That's the one problem that I do remember.)

randy

--- In MPC500@..., "fivefifteensystems" <dreas_stk@r...>
wrote:
>
> Has anyone seen an update to this checklist?
>
> Dan
>
> MPC555 HARDWARE DESIGN CHECKLIST
> The following HARDWARE CHECKLIST for designing with the MPC555.
> By Thomas Walter  8/28/2000
>






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-----------------------------------------------------------
To learn more about Freescale Microcontrollers, please visit
http://www.freescale.com/mcu


 
Yahoo! Groups Links

<*> To visit your group on the web, go to:
    http://groups.yahoo.com/group/MPC500/

<*> To unsubscribe from this group, send an email to:
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[Pete James]

Hi all,

We have a problem with a MPC566 based ECU. We have manufactured several
batches of this product with no problems. The latest batch freeze at
temperatures over 80 degrees C. The MPC566 part is an MZ part so should
be good for 125 degrees.

We have checked all the supplies and they are correct.

PORESET is stable (not asserted)
HRESET is flicking up and down - presumably causing the reset of the
part, and generated internally

When the ambient temperature falls below 80 degrees the part runs
normally again. We have nothing connected to the HRESET line other than
the pull up resistor.

Any thoughts and help would be appreciated. It's baffling us as previous
batches have worked with no problems.

Best regards
Pete

Pete James
Technical Specialist/Chief Engineer - Electronics & Software
Prodrive
Kenilworth
Warwickshire
CV8 1NR
UK
DDI - [phone]
Email - pjames@...

[Dobbin Allan-r11834]

I remember previous posts about he the value of the HRESET resistor i.e.
reducing from 10K to 4.7k or 1k.  Could you please search previous posts
forthis and see if it gives any improvement?  What value of R are you
using?
 
- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of Pete James
Sent: Monday, November 24, 2008 5:14 AM
To: MPC500@...
Subject: [MPC500] MPC565 hanging at temperature



Hi all,

We have a problem with a MPC566 based ECU. We have manufactured several
batches of this product with no problems. The latest batch freeze at
temperatures over 80 degrees C. The MPC566 part is an MZ part so should
be good for 125 degrees.

We have checked all the supplies and they are correct.

PORESET is stable (not asserted)
HRESET is flicking up and down - presumably causing the reset of the
part, and generated internally

When the ambient temperature falls below 80 degrees the part runs
normally again. We have nothing connected to the HRESET line other than
the pull up resistor.

Any thoughts and help would be appreciated. It's baffling us as previous
batches have worked with no problems.

Best regards
Pete

Pete James
Technical Specialist/Chief Engineer - Electronics & Software
Prodrive
Kenilworth
Warwickshire
CV8 1NR
UK
DDI - [phone]
Email - pjames@... <mailto:pjames%40prodrive.com>


 


[Non-text portions of this message have been removed]

[Pete James]

Thank you Allan,
 
I did check through earlier posts looking for clues, but didn't come up
with anything. Our PU resistors are 1K on both PORESET, HRESET and
SRESET.
 
We let the unit cool down and it starts up again. I've looked at the RSR
and no PO reset has occurred but both EHRS and SWRS have occurred. We
don't know though whether the watchdog reset is the cause or effect.
I.e. which one occurred first.
 
Regards
Pete

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of Dobbin Allan
Sent: 24 November 2008 15:54
To: MPC500@...
Subject: RE: [MPC500] MPC565 hanging at temperature



I remember previous posts about he the value of the HRESET resistor i.e.
reducing from 10K to 4.7k or 1k. Could you please search previous posts
forthis and see if it gives any improvement? What value of R are you
using?

- Allan

________________________________

From: MPC500@... <mailto:MPC500%40yahoogroups.com>
[mailto:MPC500@... <mailto:MPC500%40yahoogroups.com> ] On
Behalf
Of Pete James
Sent: Monday, November 24, 2008 5:14 AM
To: MPC500@... <mailto:MPC500%40yahoogroups.com>
Subject: [MPC500] MPC565 hanging at temperature

Hi all,

We have a problem with a MPC566 based ECU. We have manufactured several
batches of this product with no problems. The latest batch freeze at
temperatures over 80 degrees C. The MPC566 part is an MZ part so should
be good for 125 degrees.

We have checked all the supplies and they are correct.

PORESET is stable (not asserted)
HRESET is flicking up and down - presumably causing the reset of the
part, and generated internally

When the ambient temperature falls below 80 degrees the part runs
normally again. We have nothing connected to the HRESET line other than
the pull up resistor.

Any thoughts and help would be appreciated. It's baffling us as previous
batches have worked with no problems.

Best regards
Pete

Pete James
Technical Specialist/Chief Engineer - Electronics & Software
Prodrive
Kenilworth
Warwickshire
CV8 1NR
UK
DDI - [phone]
Email - pjames@... <mailto:pjames%40prodrive.com>
<mailto:pjames%40prodrive.com>

[Non-text portions of this message have been removed]



 


[Non-text portions of this message have been removed]