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Machine Check exception during bootup
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Machine Check exception during bootup
by Neelkanth Natu
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Hi, I was seeing machine check exception with the 'TLB Shutdown' bit set in the Status register during bootup. This would happen about 30% of the time at exactly the same place in Mips_TLBUpdate(). I was able to track this down to a bug in Mips_TLBFlush() which was using whatever address happened to be in the EntryHi register to initialize the TLB. If this address happened to be one that the system would subsequently instantiate in the TLB we would hit a machine check exception in Mips_TLBUpdate(). At first glance it appears that the code in Mips_TLBUpdate() should deal with this since it does a TLB probe and if the probe is successful it will do a 'tlbwi' to avoid the machine check. But 'tlbp' can only look at the 'asid' and 'vpn2' fields to do its job - it does not know if you are planning to install a TLB entry with 'Global' scope. IMO this is why we trip up on a machine check exception at the 'tlbwr' instruction in Mips_TLBUpdate(). I am attaching the diff to tlb.S that fixes this problem. best Neel ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== @@ -81,14 +81,14 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 -#define PAGE_SHIFT 34 +#define PAGE_SHIFT 12 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 -#define PAGE_SHIFT 2 +#define PAGE_SHIFT 12 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -232,22 +232,30 @@ mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address _MFC0 t0, COP_0_TLB_HI # Save the PID - _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 + li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + addu v0, t3 /* * Align the starting value (t1) and the upper bound (a0). */ 1: mtc0 t1, COP_0_TLB_INDEX # Set the index register. ITLBNOPFIX - _MTC0 t0, COP_0_TLB_HI # Restore the PID + _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid addu t1, t1, 1 # Increment index. - addu t0, t0, 8 * 1024 + addu v0, v0, 8 * 1024 MIPS_CPU_NOP_DELAY tlbwi # Write the TLB entry. MIPS_CPU_NOP_DELAY @@ -473,7 +481,17 @@ _MFC0 t4, COP_0_TLB_HI # Get current PID move t2, a0 mfc0 t1, COP_0_TLB_WIRED + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + addu v0, t3 + mfc0 t3, COP_0_TLB_PG_MASK # save current pgMask # do {} while (t1 < t2) _______________________________________________ freebsd-mips@... mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-mips To unsubscribe, send any mail to "freebsd-mips-unsubscribe@..." |
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Re: Machine Check exception during bootup
by M. Warner Losh
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In message: <14584.70267.qm@...>
Neelkanth Natu <neelnatu@...> writes: : r02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== : @@ -81,14 +81,14 @@ : #define _MFC0 dmfc0 : #define _MTC0 dmtc0 : #define WIRED_SHIFT 34 : -#define PAGE_SHIFT 34 : +#define PAGE_SHIFT 12 : #else : #define _SLL sll : #define _SRL srl : #define _MFC0 mfc0 : #define _MTC0 mtc0 : #define WIRED_SHIFT 2 : -#define PAGE_SHIFT 2 : +#define PAGE_SHIFT 12 : #endif These are wrong. PAGE_SHIFT is supposed to be the bit position in the TLB, not the size of the page for multiplication. At least in thoery, but looking at the manual doesn't even bear that out... However, it appears it isn't used that way at all in the rest of the code. This means we should move it outside of the #ifdef, since it has nothing to do with ISA we're compiling for. : .set noreorder # Noreorder is default style! : #if defined(ISA_MIPS32) : @@ -232,22 +232,30 @@ : mtc0 zero, COP_0_STATUS_REG # Disable interrupts : ITLBNOPFIX : mfc0 t1, COP_0_TLB_WIRED : - li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address : _MFC0 t0, COP_0_TLB_HI # Save the PID : : - _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid : _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. : _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. : mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. : + : + # : + # Load invalid entry, each TLB entry should have it's own bogus : + # address calculated by following expression: : + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; : + # One bogus value for every TLB entry might cause MCHECK exception : + # : + sll t3, t1, PAGE_SHIFT + 1 : + li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address : + addu v0, t3 I'll note that NetBSD doesn't add the 0x0fff0000 on the end here. I don't understand why we do it, even though I likely added this to the port. Does it work without it? Warner _______________________________________________ freebsd-mips@... mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-mips To unsubscribe, send any mail to "freebsd-mips-unsubscribe@..." |
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Re: Machine Check exception during bootup
by M. Warner Losh
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In message: <646809.32414.qm@...>
Neelkanth Natu <neelnatu@...> writes: : : Hi Warner, : : Thanks for reviewing the diff. : : I have made the changes you suggested in the review. The new diffs are : at the end of this email. : : - No need to have redefine PAGE_SIZE in tlb.S. I am now generating : this macro via genassym.c : : - Remove the offset 0x0fff0000 used when invalidating tlb entries. I have : tested this on MALTA as well as SWARM and it seems to work fine. Yes. You fixed the real bug, I think, when you moved from KSEG3 to KSEG0. I think there's still some things wrong with some of these routines. I'll send what I have, if I have something better, in a few. I think this is an excellent start. : best : Neel : : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c ==== : 93a94 : > ASSYM(PAGE_SHIFT, PAGE_SHIFT); : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== : 84d83 : < #define PAGE_SHIFT 34 Can you resend as a unified diff? Warner : 91d89 : < #define PAGE_SHIFT 2 : 235d232 : < li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address : 238d234 : < _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid : 241a238,247 : > : > # : > # Load invalid entry, each TLB entry should have it's own bogus : > # address calculated by following expression: : > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; : > # One bogus value for every TLB entry might cause MCHECK exception : > # : > sll t3, t1, PAGE_SHIFT + 1 : > li v0, MIPS_KSEG0_START # invalid address : > addu v0, t3 : 248c254 : < _MTC0 t0, COP_0_TLB_HI # Restore the PID : --- : > _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid : 250c256 : < addu t0, t0, 8 * 1024 : --- : > addu v0, v0, 8 * 1024 : 292c298 : < li t1, MIPS_KSEG0_START + 0x0fff0000 : --- : > li t1, MIPS_KSEG0_START : 297c303 : < # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; : --- : > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; : 476c482,492 : < li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address : --- : > : > # : > # Load invalid entry, each TLB entry should have it's own bogus : > # address calculated by following expression: : > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; : > # One bogus value for every TLB entry might cause MCHECK exception : > # : > sll t3, t1, PAGE_SHIFT + 1 : > li v0, MIPS_KSEG0_START # invalid address : > addu v0, t3 : > : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/swtch.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/swtch.S ==== : 84d83 : < #define PAGE_SHIFT 34 : 91d89 : < #define PAGE_SHIFT 2 : 364c362 : < li t1, MIPS_KSEG0_START + 0x0fff0000 # invalidate tlb entry : --- : > li t1, MIPS_KSEG0_START # invalidate tlb entry : : : --- On Wed, 7/1/09, M. Warner Losh <imp@...> wrote: : : > From: M. Warner Losh <imp@...> : > Subject: Re: Machine Check exception during bootup : > To: neelnatu@... : > Cc: freebsd-mips@... : > Date: Wednesday, July 1, 2009, 7:39 AM : > In message: <14584.70267.qm@...> : > Neelkanth Natu : > <neelnatu@...> : > writes: : > : : > r02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S : > ==== : > : @@ -81,14 +81,14 @@ : > : #define _MFC0 : > dmfc0 : > : #define _MTC0 : > dmtc0 : > : #define WIRED_SHIFT 34 : > : -#define PAGE_SHIFT 34 : > : +#define PAGE_SHIFT 12 : > : #else : > : #define _SLL sll : > : #define _SRL : > srl : > : #define _MFC0 : > mfc0 : > : #define _MTC0 : > mtc0 : > : #define WIRED_SHIFT 2 : > : -#define PAGE_SHIFT 2 : > : +#define PAGE_SHIFT 12 : > : #endif : > : > These are wrong. PAGE_SHIFT is supposed to be the bit : > position in the : > TLB, not the size of the page for multiplication. At : > least in thoery, : > but looking at the manual doesn't even bear that out... : > : > However, it appears it isn't used that way at all in the : > rest of the : > code. This means we should move it outside of the : > #ifdef, since it : > has nothing to do with ISA we're compiling for. : > : > : .set : > noreorder : > # Noreorder is default style! : > : #if defined(ISA_MIPS32) : > : @@ -232,22 +232,30 @@ : > : mtc0 zero, : > COP_0_STATUS_REG # : > Disable interrupts : > : ITLBNOPFIX : > : mfc0 t1, : > COP_0_TLB_WIRED : > : - li v0, : > MIPS_KSEG3_START + 0x0fff0000 # invalid address : > : _MFC0 t0, : > COP_0_TLB_HI # Save the : > PID : > : : > : - _MTC0 v0, : > COP_0_TLB_HI # Mark : > entry high as invalid : > : _MTC0 zero, : > COP_0_TLB_LO0 # Zero : > out low entry0. : > : _MTC0 zero, : > COP_0_TLB_LO1 # Zero : > out low entry1. : > : mtc0 zero, : > COP_0_TLB_PG_MASK # Zero out mask entry. : > : + : > : + # : > : + # Load invalid entry, each TLB entry : > should have it's own bogus : > : + # address calculated by following : > expression: : > : + # MIPS_KSEG0_START + 0x0fff0000 + 2 * : > i * PAGE_SIZE; : > : + # One bogus value for every TLB entry : > might cause MCHECK exception : > : + # : > : + sll t3, t1, : > PAGE_SHIFT + 1 : > : + li v0, : > MIPS_KSEG0_START + 0x0fff0000 # invalid : > address : > : + addu v0, t3 : > : > I'll note that NetBSD doesn't add the 0x0fff0000 on the end : > here. I : > don't understand why we do it, even though I likely added : > this to the : > port. Does it work without it? : > : > Warner : > : : : : : _______________________________________________ freebsd-mips@... mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-mips To unsubscribe, send any mail to "freebsd-mips-unsubscribe@..." |
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Re: Machine Check exception during bootup
by M. Warner Losh
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In message: <122643.47019.qm@...>
Neelkanth Natu <neelnatu@...> writes: : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c ==== : @@ -91,6 +91,7 @@ : ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); : ASSYM(SIGFPE, SIGFPE); : ASSYM(PGSHIFT, PGSHIFT); : +ASSYM(PAGE_SHIFT, PAGE_SHIFT); : ASSYM(NBPG, NBPG); : ASSYM(SEGSHIFT, SEGSHIFT); : ASSYM(NPTEPG, NPTEPG); How do PAGE_SHIFT and PGSHIFT differ? Warner _______________________________________________ freebsd-mips@... mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-mips To unsubscribe, send any mail to "freebsd-mips-unsubscribe@..." |
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Re: Machine Check exception during bootup
by M. Warner Losh
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In message: <385015.11949.qm@...>
Neelkanth Natu <neelnatu@...> writes: : : Hi Warner, : : --- On Fri, 7/3/09, M. Warner Losh <imp@...> wrote: : : > From: M. Warner Losh <imp@...> : > Subject: Re: Machine Check exception during bootup : > To: neelnatu@... : > Cc: freebsd-mips@... : > Date: Friday, July 3, 2009, 8:11 PM : > In message: <122643.47019.qm@...> : > Neelkanth Natu : > <neelnatu@...> : > writes: : > : ==== : > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 : > - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c : > ==== : > : @@ -91,6 +91,7 @@ : > : ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); : > : ASSYM(SIGFPE, SIGFPE); : > : ASSYM(PGSHIFT, PGSHIFT); : > : +ASSYM(PAGE_SHIFT, PAGE_SHIFT); : > : ASSYM(NBPG, NBPG); : > : ASSYM(SEGSHIFT, SEGSHIFT); : > : ASSYM(NPTEPG, NPTEPG); : > : > How do PAGE_SHIFT and PGSHIFT differ? : : They are identical. I looked at other architectures and it seems that : PGSHIFT is a macro defined for mips alone. The same is true for : PGOFSET and PAGE_MASK. : : So I went with the obvious macro - PAGE_SHIFT. : : I think we should toast PGSHIFT and PGOFFSET and replace them with : PAGE_SHIFT and PAGE_MASK respectively. What do you think? This sounds like a good cleanup item... Warner _______________________________________________ freebsd-mips@... mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-mips To unsubscribe, send any mail to "freebsd-mips-unsubscribe@..." |
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