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Thread (777 Threads) Rating Replies Last Message

CRC generator by anulekha.aeranki
4
by OutputLogic

A Question by sara karami
1
by David Cary

Re: A Question by thomas_rudloff
1
by Morteza Shokri

Peripherals On Demand by Fabien Marteau-2
2
by Fabien Marteau-2

OpenCores-related internships? by Wojciech A. Koszek-4
0
by Wojciech A. Koszek-4

UART 16550 Addressing by chris.reeg
2
by Mark McDougall

Cycle accurate modeling ORPSoC with Verilator by Jeremy Bennett-4
0
by Jeremy Bennett-4

Plasma/Xilinx problem by magnus.wedmark
3
by magnus.wedmark

Re: Re: I2C syntax error in Synopsys by nitylles
1
by Richard Herveille

Re: Re: I2C syntax error in Synopsys by nitylles
0
by nitylles

Re: uClinux on Plasma by magnus.wedmark
1
by djd328

New version of VHCG released by sheng zhu
0
by sheng zhu

uClinux on Plasma by Texblues
0
by Texblues

GPL License - again by motilito
16
by Rick Collins-3

MII mac verilog module by Amir Yanai
1
by motilito

GPL License - again by Víctor López-3
0
by Víctor López-3

T80 core - NoIce Debugger Problem by Antus Tibor
0
by Antus Tibor

UART16750 by Sebastian Witt-2
0
by Sebastian Witt-2

I2c-ocore linux driver debug by Fabien Marteau
2
by Peter Korsgaard-2

Can bus by osquillar
0
by osquillar

Re: opb2wb by osquillar
0
by osquillar

verilog UART 16550 BFM simulation problem by valluri_sathish
1
by valluri_sathish

Help with a coregen wishbone wrapper by Newell Jensen-2
0
by Newell Jensen-2

Wishbone LPC Host & Peripheral - interrupts? by Mark McDougall
3
by Howard Harte

C to Verilog core generator by nadav256
0
by nadav256

T80 Core x by ronivon.costa
14
by Alessandro-42

Re: the errors of "tests.v" module? by jinsongq
0
by jinsongq

VHCG is updated! by sheng zhu
0
by sheng zhu

Re: CRC32 Calculation by ashish228
1
by Umair Siddiqui

opb2wb by osquillar
2
by osquillar

FPU comparison by Klemen Dovrtel
0
by Klemen Dovrtel

I2C controller core by thomas.roesler
9
by Richard Herveille

OCIDEC-3. by rff_tech
5
by Mark McDougall

wishbone_bfm example by Klemen Dovrtel
4
by Richard Herveille

VHDL 16550 UART core - strange tx signal by Klemen Dovrtel
2
by Klemen Dovrtel
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