Nabble - OpenCores

RE: I2C controller core

2009-11-29T20:56:21Z

Hi,
I'm beginner to FPGA.I have some questions about I2C controller core.I'm confusing those signals like wb_cyc_i,wb_ack_o,i2c_al,arst_i and wb_rst_i.Can anyone explain them to me?Thanks in advance.
------------------------------------

Richard Herveille wrote:

Some quick answers...

#1 I recommend you use external pull-up resistors. Although the on-chip
pull-up might work as well.
If you don't initiate a transfer you don't see any activity; the SCL and SDA
lines should just remain high.

#2 The tri-state buffers are required. You have to add these at a higher
level (outside of the IP core).
The core is a wishbone slave device, which means you must use an external
master that configures the i2c IP and sends commands to it.
Out of the box the i2c IP does not do anything; it only responds to commands
from the master.

Richard

-----Original Message-----
From: cores-bounces@opencores.org [mailto:cores-bounces@opencores.org] On
Behalf Of Thomas.Roesler@hs-furtwangen.de
Sent: 10 December 2008 17:04
To: cores@opencores.org
Subject: [oc] I2C controller core

Hello everybody

im a student at a University in Germany and im trying to implement the
I2C controller core, i am not that experienced in VHDL but im doing my
best. I would appreciate if you could answer my questions.

my questions are:

1) im using the simple i2c and ts_ds1621 that is provided with the core.
This simple core should complete, so if i synthesize it and load it onto
my Basys board i should get some activity at the sda and scl lines, right?
But i am not getting any activity at all, for your information: i used a
clock divider (the core is driven by 1Hz) and send copies of the sda and
scl signals to the leds, to see whats going on (i could send you a copy
of the code if its unclear what i mean). Is there anything else i have to
do to get some acivity, cause i think i should see some activity even if
theres no ds1621 on the bus (especially at that low clock rate).
Do i need some kind of start signal to get it to work? Does the bus have
to be pulled up externally or is it enough to define it as pullup in the
user constraints file?

2) if im using the wb i2c controller core the doc says i have to add the
tri-state buffers at a higher hierarchical level. So do i have to make a
new toplevel entity that uses the original master top as component and
instantiates it, then insert these buffer there? Then i think i would have
to use some kind of Wishbone master that sends the wishbone signals
to the controller, cause i just wanna use the controller to read/write
from/to i2c devices and show the data on 7 segment leds (for now).
The wishbone part is perhaps the one i struggle, i know its great when u
combine different cores, but when you just want to use the i2c
controller its a bit too much, escpecially if your not that experienced to
the cores and wishbone, but thats just my opinion, im sure i will change
my mind later if i understand the whole concept.
could anybody perhaps give me a small example in vhdl how to make a
wishbone master to read/write from a i2c device or is that in the
wishbone documentation ( if so i must have missed sth and have to look
through it again).

best regards
Thomas Roesler

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

From forum: OpenCores - IP Cores

simulating the ORPSOC

2009-11-17T01:14:03Z

Hello I try to simulate the ORPSOC.I have installed the Icarus simulator. In the subdirectory sim i run the command make simulate and i have an error : Pas de régle pour fabriquer la cible simulate. Have you an idea about this problem? Thanks .

Nabble - OpenCores

RE: I2C controller core

simulating the ORPSOC

patching or1ksim 0.3.0 in an1

error in compiling demo_or32_sw

simulate the open risc

building and installing binutils

Barrel Shifter, you have one?

Re: CRC generator

Re: Minimal configuration for Spartan-3E Starter Kit board

ORP_SOC in Spartan-3E500

Re: : make verilate error (EAN6/ESP5 ORPSoC with Verilator)

Re: ERR: 8-bit program load out of memory area: 01000074

: make verilate error (EAN6/ESP5 ORPSoC with Verilator)

Re: make verilate error (EAN6/ESP5 ORPSoC with Verilator)

Re: orpmon

Re: Few questions about Xlinix FPGA boards.

Re: Few questions about Xlinix FPGA boards.

Re: A Question

About old version toolchain for uClinux2.0.x

Re: A Question

Few questions about Xlinix FPGA boards.

Re: Toolchain news

Re: orpmon

Re: Toolchain news

Re: Toolchain news

Re: C program interrupt handle function (AN1.pdf)

Re: C program interrupt handle function (AN1.pdf)

Re: C program interrupt handle function (AN1.pdf)

Toolchain news

Re: openrisc toolchains

Re: Building binutils 2.18.50 on Ubuntu 8.10 (gcc 4.3.2)

Re: A Question

Re: Re: Some MMU confusion

Re: C program interrupt handle function (AN1.pdf)

C program interrupt handle function (AN1.pdf)