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OpenCores

OpenCores is a loose collection of people who are interested in developing hardware, with a similar ethos to the free software movement. Currently the emphasis is on digital modules called 'cores', since FPGAs have reduced the incremental cost of a core to approximately zero. OpenCores home is here.

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OpenCores - RISC OpenCores - IP Cores OpenCores - nnARM OpenCores - USB	OpenCores - Ethernet MAC OpenCores - PCI OpenCores - Video OpenCores - Business	OpenCores - ECC OpenCores - Announce OpenCores - FPU OpenCores - Bluetooth	OpenCores - CDRom OpenCores - SoC Builder OpenCores - Montherboards
OpenCores - Announce OpenCores - Bluetooth OpenCores - Business OpenCores - CDRom	OpenCores - ECC OpenCores - Ethernet MAC OpenCores - FPU OpenCores - IP Cores	OpenCores - Montherboards OpenCores - nnARM OpenCores - PCI OpenCores - RISC	OpenCores - SoC Builder OpenCores - USB OpenCores - Video

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Thread (1894 Threads)

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compile c++ program by lsousa

1

by rich_daddio

Re: Or1ksim and tlm2.0 by Jeremy Bennett-4

3

by lsousa

instruction order by wit-3

7

by wit-3

linux-2.6.24 by rich_daddio

7

by Jeremy Bennett-4

bench folder in usb2.0 device controller is missing by ram.vibhute

1

by Chunlin Zhang-2

question about or1ksim used by embecosm's ean1.pdf and ean2.pdf by yejun.golden

10

by Jeremy Bennett-4

Openrisc Test Suite for rtl. by Zakhir Hussain

2

by Jeremy Bennett-4

is there any example for or1ksim version 3.0? by huang_fo

1

by Jeremy Bennett-4

Final Release Candidate for Or1ksim 0.3.0 by Jeremy Bennett-4

0

by Jeremy Bennett-4

problems compiling gcc-4.2.2 with or32-elf target by Gijs Molenaar-3

2

by vinut

Re: 64-bit BAR for PCI Bridge core by dk_vhd

0

by dk_vhd

error from /or1sim-2.0/testbench by huang_fo

1

by Jeremy Bennett-4

why under linux-2.6.19 by huang_fo

1

by Jeremy Bennett-4

Getting it All to Work! Problem by deutch_lerne

0

by deutch_lerne

UART 16550 Addressing by chris.reeg

2

by Mark McDougall

_mc_init_1 address in head.S by wit-3

9

by wit-3

64-bit BAR for PCI Bridge core by george.hong

1

by 王小东

Re: ubuntu 8.10 by Jeremy Bennett-4

0

by Jeremy Bennett-4

Hardware breakpoint insertion Openrisc by Raul Fajardo

1

by Jeremy Bennett-4

OpenRISC project update by marcus.erlandsson

0

by marcus.erlandsson

General implementation of rc203soc by Raul Fajardo

1

by Jeremy Bennett-4

RTL simulation: system is always IDLE by marodmo

3

by Jeremy Bennett-4

About OR1200 instruction set by KavenHuang

1

by Jeremy Bennett-4

Cycle accurate modeling ORPSoC with Verilator by Jeremy Bennett-4

0

by Jeremy Bennett-4

Cycle accurate modeling ORPSoC with Verilator by Jeremy Bennett-4

0

by Jeremy Bennett-4

OpenRISC mainlining plans ? by Florian Fainelli-5

4

by Florian Fainelli-5

I get a error when booting the linux2.6.23 by yejun.golden

0

by yejun.golden

Plasma/Xilinx problem by magnus.wedmark

3

by magnus.wedmark

Re: 100G Ethernet MAC by rich_daddio

4

by ghanashyam prabhu

Re: Re: I2C syntax error in Synopsys by nitylles

1

by Richard Herveille

10GE Mac Core status by Yanick Viens

1

by eziggurat

Re: Re: I2C syntax error in Synopsys by nitylles

0

by nitylles

Re: Fw:Re:Re: Re:Re: a error when booting the linux-2.6.23 in the xt by rich_daddio

0

by rich_daddio

Re: linux_2.6.23_or32_unified_simtested.bz2 can not download from th by rich_daddio

0

by rich_daddio

Re: booting linux - AN2 by Jeremy Bennett-4

0

by Jeremy Bennett-4

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