Openrisc Test Suite for rtl.

[Zakhir Hussain]

Hi all,

           I am trying to implement a coprocessor type support for the or1200. But after the changes I would like to verify whether all the existing functionality remains unchanged. Is there an existing test suite (for the rtls, not simulator) that i can run and see if all the testcases pass without any issues? Also pls let me know how the end result is validated ( is it by comparing the result from the simulator with same input?).

thanks a lot,
zakhir

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[Jeremy Bennett-4]

On Tue, 2009-02-24 at 21:20 -0800, Zakhir Hussain wrote:

> Hi all,
>
>            I am trying to implement a coprocessor type support for the
> or1200. But after the changes I would like to verify whether all the
> existing functionality remains unchanged. Is there an existing test
> suite (for the rtls, not simulator) that i can run and see if all the
> testcases pass without any issues? Also pls let me know how the end
> result is validated ( is it by comparing the result from the simulator
> with same input?).
>
>
>
>
> ______________________________________________________________________

Hi Zakhir,

There are a set of simulation scripts with the OpenRISC Reference
System-on-Chip (ORPSoC), which is in the or1k/orp/orp_soc directory on
CVS. I'm not aware of any other verification tests - perhaps other
readers of this mailing list can help here.

These build a SoC by adding various peripherals to the OR1200. The tests
consist of running a number of embedded programs on the RTL. You can
check for validity by ensuring you get the same result in the same
number of cycles.

However these are only a limited set of tests. They only test the
functionality of the CPU. If you add a co-processor, they could well
show the same result, because your co-processor has not been invoked.
Extending the set of tests would be very helpful.

These tests are designed for use with Cadence NC. There is an Embecosm
application note explaining how to simulate the RTL using Icarus Verilog
or by generating SystemC using Verilator.

        http://www.embecosm.com/download/ean6.html

HTH,


Jeremy

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[Jeremy Bennett-4]

On Wed, 2009-02-25 at 06:21 -0800, Zakhir Hussain wrote:
>
>      Thanks for your very valuable feedback and help. I will try
> following the link you provided. I already had a look into the cvs
> test cases, but as you mentioned, most of them focussed on the
> attached peripheral or so. I will hope fully be writing some more of
> an OR1200 instruction/pipeline based test cases to check for
> consistency and will be happy to add them to original test suite if
> all are interested.
>

Hi Zakhir,

You can never have too many tests! Any that you can add will be much
appreciated. I'll be particularly interested in pipeline tests, since
I've recently been having difficulties with getting GDB to talk to
strictly cycle accurate models due to problems in this area.

ATB,


Jeremy

(copied the whole list - I'm sure others will have good ideas of tests
that are especially needed)
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