At 04:49 AM 1/6/2009, Granville Gregg wrote:
>....My basic problem is that I am unable to run the cache....
>Several people have responded to my questions on wildrice
>e-mail group that they thought the issue was burst mode and
>that I may have some lines wrong that is why I have included
>the Figures in the e-mail....
I can't speak from experience about the V4 core, but I have seen
similar issues with the MCF5307 in past projects. It isn't
unusual to find that single word-sized reads and writes work just
fine because the bus cycles leave lots of cushion around the
single transfer, but burst mode has much stronger requirements
and will fail if the DRAM configuration isn't correct. The nature
of the failure can be informative as well.
In your memory test, you can validate that burst mode works by
using a MOVEM instruction to operate on enough registers to match
a multiple of the size of a cache line. (16 bytes or 4 registers
on the 5307, I don't know about your V4 CPU.) I'd recommend using
distinct values in each byte of each register so that the actual
values read back might provide some hints about the nature of the
timing mistake.
For my 5307 project I did something like this, where A0 is
pointing into the appropriate patch of DRAM and cache-line aligned:
move.l #$00010203,d0
move.l #$10111213,d1
move.l #$20212223,d2
move.l #$30313233,d3
movem /d0-d3/,@A0
move.l 0(A0),d0
move.l 4(A0),d1
move.l 8(A0),d2
move.l 12(A0),d3
after which d0..d3 should be unchanged, which would prove that
writing a 4-longword burst had correct timing. I then reversed
the reads and writes:
move.l #$00010203,d0
move.l #$10111213,d1
move.l #$20212223,d2
move.l #$30313233,d3
move.l d0,0(A0)
move.l d1,4(A0)
move.l d2,8(A0)
move.l d3,12(A0)
movem @a0,/d0-d3/
to prove that a reading a 4-longword burst also had correct timing.
Ross Berteig
Ross@...
Cheshire Engineering Corp.
http://www.CheshireEng.com/+1 626 351 5493
+1 626 351 8645 FAX
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