As Scott and others have hinted at before - you can do almost anything
on a PIC in 12 instructions - HiTech is trying hard - someday they hope
to get CLRF up to 12 instructions but for now it's only 5 :)
HiTech changed when Clyde hired a new president. That's when I stoppped
my maintenance contract with them.
Now that Microchip owns HiTech, perhaps things will change. I imagine
the Microchip forums would be a place to look, there might be chatter
about it.
Cheers,
Bob
Mike Harrison wrote:
> (posted before but forgot tag....)
>
> WTF is going on with the Hi-Tech compiler that ships with MPLAB....
> A few samples below (all vars are global chars)., target 16F818
>
> Can anyone think of any explanation for such poor code generation other than deliberately making it
> slow to make their paid-for compiler look better ?
>
> It can't be doing Microchip any favours shipping such a poor performing compiler with MPLAB as it
> makes their chips look slow and inefficient.
>
>
> 365: irrxsum1+=irbyte1;
> 115 087A MOVF 0x7a, W
> 116 00C3 MOVWF 0x43
> 117 0843 MOVF 0x43, W
> 118 07F4 ADDWF 0x74, F
>
> Should be 2 instructions
>
> 366: ircnt1=0;
> 119 1003 BCF 0x3, 0
> 11A 3000 MOVLW 0
> 11B 1803 BTFSC 0x3, 0
> 11C 3001 MOVLW 0x1
> 11D 00FB MOVWF 0x7b
>
> This is especially bizarre - should be 1 CLRF instruction
>
> 349: irtmr1+=bittime2; // bittime2 is a constant
> 0DF 300E MOVLW 0xe
> 0E0 00C3 MOVWF 0x43
> 0E1 0843 MOVF 0x43, W
> 0E2 07F5 ADDWF 0x75, F
>
> Should be 2 instructions
>
>
> 350: ircnt1++;
> 0E3 3001 MOVLW 0x1
> 0E4 00C3 MOVWF 0x43
> 0E5 0843 MOVF 0x43, W
> 0E6 07FB ADDWF 0x7b, F
>
> Should be 1 INCF instruction
>
> 322: irin=PORTA;
> 090 0805 MOVF 0x5, W
> 091 00C3 MOVWF 0x43
> 092 0843 MOVF 0x43, W
> 093 00FC MOVWF 0x7c
>
> Why is it storing in two places?
>
--
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
