Re: 16-bit code and L4

[Marcus Voelp]

Hi Valery,

Valery V. Sedletski wrote:
> So, the questions are:
>
> 1) There is L4Linux. It is mostly 32-bit. But as I know, the Linux kernel also contains some 16-bit parts, such as setup code (it
> works with BIOS routines and probes hardware), and also (as I heard) acpi suspend/wakeup code. So, it contains 16-bit
> segments. But doesn't it interfere with L4? How did the people porting Linux to the L4 microkernel solve the problem of 16-bit
> code? And doesn't it interfere with ELF format capabilities (it is pure 32/64-bit, as I understand)?
>  
The parts of 16-bit code in the Linux kernel are primarily to bootstrap
the system and to bring it up again from deep sleep modes. In L4Linux,
the microkernel does most of this job. So there is no need to run these
parts in L4Linux anymore and they have thus been removed during the porting.

> 2) Must all the segment registers be CS == DS == ES == FS == GS == SS == FLAT in L4 usermode programs (in Intel
> architecture implementation)? Or, there exist a possibility to use segments other than FLAT?
>  
Fiasco preserves some of these segments (e.g., GS to support thread
local storage). However, unless OS/2 makes use of these segments in
32-bit mode there is no need to change these from a flat setting.
> 3) Is it possible to cause the L4 kernel to create 16-bit segment descriptor on Intel architecture?
>  
What you are looking for is microkernel support for the virtual x86
mode. Unfortunately, only the old L4 assembler kernels supported this
processor mode and these are no longer supported. If you really want to
run the 16-bit code on bare metal (and not in something like qemu) you
probably need to add support for VM86 into the kernel (e.g., by adding
an architecture specific systemcall which executes some code in VM86
mode and which returns with any abnormalities to a 32-bit exception
handler).

Best regards

    Marcus

--
Marcus Völp

Technische Universität Dresden
Department of Computer Science
Institute for System Architecture

Tel: [phone]
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Email: voelp@...
Web: http://os.inf.tu-dresden.de/~voelp

[Valery V. Sedletski]

>>> 2) Must all the segment registers be CS == DS == ES == FS == GS == SS == FLAT in L4 usermode
>programs (in Intel
>>> architecture implementation)? Or, there exist a possibility to use segments other than FLAT?
>>>  
>>Fiasco preserves some of these segments (e.g., GS to support thread
>>local storage). However, unless OS/2 makes use of these segments in
>>32-bit mode there is no need to change these from a flat setting.
>
>It seems, that OS/2 does not use GS (GS seems to be always == 0), at least, in application programs.
>

But also FS is used to address a structure named Thread Info Block (TIB), it is also not flat (it has a limit=0x30)
So, FS is used by OS/2 and programs depend on it. GS seems to be not used, and ES and DS are generally
flat.

[Adam Lackorzynski]

On Thu Jun 21, 2007 at 03:55:24 +1300, Valery V. Sedletski wrote:

> >>> 2) Must all the segment registers be CS == DS == ES == FS == GS == SS == FLAT in L4 usermode
> >programs (in Intel
> >>> architecture implementation)? Or, there exist a possibility to use segments other than FLAT?
> >>>  
> >>Fiasco preserves some of these segments (e.g., GS to support thread
> >>local storage). However, unless OS/2 makes use of these segments in
> >>32-bit mode there is no need to change these from a flat setting.
> >
> >It seems, that OS/2 does not use GS (GS seems to be always == 0), at least, in application programs.
> >
>
> But also FS is used to address a structure named Thread Info Block
> (TIB), it is also not flat (it has a limit=0x30) So, FS is used by
> OS/2 and programs depend on it. GS seems to be not used, and ES and DS
> are generally flat.

Fiasco makes some GDT slots available to userland so that FS and GS can
be used with those.



Adam
--
Adam                 adam@...
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/