On Sat, 2006-03-18 at 15:36 +0100, Arnim Laeuger wrote:
> Hi!
>
> > Any idea why "The Wishbone clock must be at least 2x bit_clk_pad_i"?
>
> This is my interpretation of the circuit built around bit_clk_r in
> ac97_soc.v. bit_clk_r samples the AC97 clock on bit_clk_pad_i with the
> Wishbone clock. This can only work reliably when wclk has at least
> twice the frequency of the sampled signal.
...
> Cheers
>
> Arnim
Arnim,
why don't you publish your modifications that you previously
emailed me ? I think they might be helpful to others as well.
Best Regards,
rudi
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Rudolf Usselmann, ASICS World Services,
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