>>> Any idea why "The Wishbone clock must be at least 2x
>>> bit_clk_pad_i"?
>>
>> This is my interpretation of the circuit built around bit_clk_r in
>> ac97_soc.v. bit_clk_r samples the AC97 clock on bit_clk_pad_i with
>> the Wishbone clock. This can only work reliably when wclk has at
>> least twice the frequency of the sampled signal.
>
>
> Arnim,
>
> why don't you publish your modifications that you previously emailed
> me ? I think they might be helpful to others as well.
I've uploaded the modified ac97_soc.v to
http://home.mnet-online.de/al/ac97_soc.vThe changes work fine for my designs at the moment. I.e. the suspend
detection circuit doesn't reinitialize the AC97 link periodically.
However, it's worth mentioning that my application doesn't deal with
intentional suspend at all. So the modification is not tested against
this scenario.
For integration details refer to the project files at
http://home.freeuk.com/fpgaarcade/cv.htmBest regards
Arnim
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