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Re: ATLAS 3.8.3 released
by Michael Abshoff-3
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On Fri, Feb 20, 2009 at 1:10 PM, Clint Whaley <whaley@...> wrote:
> Michael,
Hi Clint,
>>While applying my patches I was glad to see that many fixes from 3.9.x
>>that I used in Sage's 3.8.2 were backported. But I noticed that in
>>archinfo_x86.c you did not add the "case 6" for the Pentium IV models
>>while the missing CPU IDs for the various other missing CPUs you had
>>listed at the errata page were added. The "case 6" are Pentium Ds IIRC
>>or maybe some P IV base Extreme Edition Intel CPU IIRC.
>
> OK, the reason this didn't get backported is that it is not in the 3.9.x
> series either. This means that I was unaware of it. Now, in perfect
> world, that would mean nobody had informed me that configure needed to
> be amended, but I'm guessing you are going to tell me that I lost some
> mail or forgot about a bug/support tracker item somewhere?
Well, it was on the errata page according to
http://trac.sagemath.org/sage_trac/ticket/3787 at some point:
Note the the remark I added "And I figure it is better to quote the
solution since the errata page tends to get updated quite a bit:"
followed by
[quote]
To fix this, simply comment out lines 95 and 99 of ATLAS/CONFIG/src/backend
/archinfo_x86.c. So, change line 95 from:
if (*family == 0xf || *family == 0) /* extended family is added in */
to:
/* if (*family == 0xf || *family == 0)*/ /* extended family is added in */
and change line 99 from
if (*model == 0xf) /* extended model is concatenated */
to:
/* if (*model == 0xf)*/ /* extended model is concatenated */
Essentially, all the Core2-based systems are treated the same by ATLAS. So,
to get to use the architectural defaults on Core2-based XEONs, change line
297 from:
case 15:
to:
case 15: ; case 23:
Finally, to enable better P4E identification, change line 313 from:
case 4:
to:
case 4: ; case 6:
[end quote]
So unless your evil twin edited the page this got somehow lost.
> Thanks
> Clint
Anyway, I am having two things I am currently interested in:
* Itanium CPU identification. This CPU:
processor : 3
vendor : GenuineIntel
arch : IA-64
family : Itanium 2
model : 0
revision : 7
archrev : 0
features : branchlong, 16-byte atomic ops
cpu number : 0
cpu regs : 4
cpu MHz : 1594.000733
itc MHz : 399.181840
BogoMIPS : 3186.68
siblings : 2
physical id: 3
core id : 1
thread id : 0
Running either RHEL 5 or SLES 10 is misidentified as a Itanium with
standard ATLAS 3.8.3. I haven't poked around in the detection routines
yet, but ATLAS might be missing a couple CPUids. For now I just force
every Itanium to be an Itanium 2. Give the number of Itaniums in the
wild I haven't heard any complaints yet :)
* The other issue concerns selecting a maximum SSE level. Right now I
can pick some Arch, but the SSE level up to SSE3 (==PNI) is determined
by the probes. So even if I pick a PIII for example I end up with SSE3
support if the CPU supplies it. So far the trick I am using is to have
the SSE probe unconditionally return "FAILURE", so that for example I
get a SSE2 only ATLAS on a CPU with SSE3 or more. Obviously
performance will suck, but in case of Sage it is between "illegal
instructions" and working binaries, so performance is something I can
sacrifice for that.
Is there a plan to make the SSE level selectable as a config option?
Cheers,
Michael
> **************************************************************************
> ** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
> **************************************************************************
>
> ------------------------------------------------------------------------------
> Open Source Business Conference (OSBC), March 24-25, 2009, San Francisco, CA
> -OSBC tackles the biggest issue in open source: Open Sourcing the Enterprise
> -Strategies to boost innovation and cut costs with open source participation
> -Receive a $600 discount off the registration fee with the source code: SFAD
> http://p.sf.net/sfu/XcvMzF8H
> _______________________________________________
> Math-atlas-devel mailing list
> Math-atlas-devel@...
> https://lists.sourceforge.net/lists/listinfo/math-atlas-devel
>
------------------------------------------------------------------------------
Open Source Business Conference (OSBC), March 24-25, 2009, San Francisco, CA
-OSBC tackles the biggest issue in open source: Open Sourcing the Enterprise
-Strategies to boost innovation and cut costs with open source participation
-Receive a $600 discount off the registration fee with the source code: SFAD
http://p.sf.net/sfu/XcvMzF8H
_______________________________________________
Math-atlas-devel mailing list
Math-atlas-devel@...
https://lists.sourceforge.net/lists/listinfo/math-atlas-devel
> Michael,
Hi Clint,
>>While applying my patches I was glad to see that many fixes from 3.9.x
>>that I used in Sage's 3.8.2 were backported. But I noticed that in
>>archinfo_x86.c you did not add the "case 6" for the Pentium IV models
>>while the missing CPU IDs for the various other missing CPUs you had
>>listed at the errata page were added. The "case 6" are Pentium Ds IIRC
>>or maybe some P IV base Extreme Edition Intel CPU IIRC.
>
> OK, the reason this didn't get backported is that it is not in the 3.9.x
> series either. This means that I was unaware of it. Now, in perfect
> world, that would mean nobody had informed me that configure needed to
> be amended, but I'm guessing you are going to tell me that I lost some
> mail or forgot about a bug/support tracker item somewhere?
Well, it was on the errata page according to
http://trac.sagemath.org/sage_trac/ticket/3787 at some point:
Note the the remark I added "And I figure it is better to quote the
solution since the errata page tends to get updated quite a bit:"
followed by
[quote]
To fix this, simply comment out lines 95 and 99 of ATLAS/CONFIG/src/backend
/archinfo_x86.c. So, change line 95 from:
if (*family == 0xf || *family == 0) /* extended family is added in */
to:
/* if (*family == 0xf || *family == 0)*/ /* extended family is added in */
and change line 99 from
if (*model == 0xf) /* extended model is concatenated */
to:
/* if (*model == 0xf)*/ /* extended model is concatenated */
Essentially, all the Core2-based systems are treated the same by ATLAS. So,
to get to use the architectural defaults on Core2-based XEONs, change line
297 from:
case 15:
to:
case 15: ; case 23:
Finally, to enable better P4E identification, change line 313 from:
case 4:
to:
case 4: ; case 6:
[end quote]
So unless your evil twin edited the page this got somehow lost.
> Thanks
> Clint
Anyway, I am having two things I am currently interested in:
* Itanium CPU identification. This CPU:
processor : 3
vendor : GenuineIntel
arch : IA-64
family : Itanium 2
model : 0
revision : 7
archrev : 0
features : branchlong, 16-byte atomic ops
cpu number : 0
cpu regs : 4
cpu MHz : 1594.000733
itc MHz : 399.181840
BogoMIPS : 3186.68
siblings : 2
physical id: 3
core id : 1
thread id : 0
Running either RHEL 5 or SLES 10 is misidentified as a Itanium with
standard ATLAS 3.8.3. I haven't poked around in the detection routines
yet, but ATLAS might be missing a couple CPUids. For now I just force
every Itanium to be an Itanium 2. Give the number of Itaniums in the
wild I haven't heard any complaints yet :)
* The other issue concerns selecting a maximum SSE level. Right now I
can pick some Arch, but the SSE level up to SSE3 (==PNI) is determined
by the probes. So even if I pick a PIII for example I end up with SSE3
support if the CPU supplies it. So far the trick I am using is to have
the SSE probe unconditionally return "FAILURE", so that for example I
get a SSE2 only ATLAS on a CPU with SSE3 or more. Obviously
performance will suck, but in case of Sage it is between "illegal
instructions" and working binaries, so performance is something I can
sacrifice for that.
Is there a plan to make the SSE level selectable as a config option?
Cheers,
Michael
> **************************************************************************
> ** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
> **************************************************************************
>
> ------------------------------------------------------------------------------
> Open Source Business Conference (OSBC), March 24-25, 2009, San Francisco, CA
> -OSBC tackles the biggest issue in open source: Open Sourcing the Enterprise
> -Strategies to boost innovation and cut costs with open source participation
> -Receive a $600 discount off the registration fee with the source code: SFAD
> http://p.sf.net/sfu/XcvMzF8H
> _______________________________________________
> Math-atlas-devel mailing list
> Math-atlas-devel@...
> https://lists.sourceforge.net/lists/listinfo/math-atlas-devel
>
------------------------------------------------------------------------------
Open Source Business Conference (OSBC), March 24-25, 2009, San Francisco, CA
-OSBC tackles the biggest issue in open source: Open Sourcing the Enterprise
-Strategies to boost innovation and cut costs with open source participation
-Receive a $600 discount off the registration fee with the source code: SFAD
http://p.sf.net/sfu/XcvMzF8H
_______________________________________________
Math-atlas-devel mailing list
Math-atlas-devel@...
https://lists.sourceforge.net/lists/listinfo/math-atlas-devel
« Return to Thread: ATLAS 3.8.3 released
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