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Re: ATLAS 3.8.3 released

by Michael Abshoff-3 :: Rate this Message:

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On Fri, Feb 20, 2009 at 5:00 PM, Clint Whaley <whaley@...> wrote:

Hi Clint.

>> So unless your evil twin edited the page this got somehow lost.
>>It is actually still there right at the top of
>> http://math-atlas.sourceforge.net/errata3.8.2.html
>>I missed it while I searched for it for some strange reason :)
>
> OK, I seem to have made all the other changes for that errata, so it looks
> like I simply overlooked the case 6 change . . .

Well, I can understand how something like that can slip by on
occasion. I have done it often enough myself in Sage :)

>>Anyway, I am having two things I am currently interested in:
>>
>> * Itanium CPU identification. This CPU:
>
>>processor  : 3
>>vendor     : GenuineIntel
>>arch       : IA-64
>>family     : Itanium 2
>>model      : 0
>>revision   : 7
>>archrev    : 0
>>Running either RHEL 5 or SLES 10 is misidentified as a Itanium with
>>standard ATLAS 3.8.3. I haven't poked around in the detection routines
>>yet, but ATLAS might be missing a couple CPUids. For now I just force
>>every Itanium to be an Itanium 2. Give the number of Itaniums in the
>>wild I haven't heard any complaints yet :)
>
> My guess is ATLAS is just parsing the cpuinfo file incorrectly (I don't
> think archinfo_x86 works there, so we are stuck with the OS-specific tricks).
> If you want to submit a patch on that, I'll be happy to fix . . .

Ok, let me come up with a cleaner fix and post it to the support
tracker. I also never reliably got it to work that gcc ought to not
use "-m64" for gcc on Itanium even though that special case is in the
code after I corrected the detection problem, so I will look at that
again in the same go since right now I just insert a two line special
case to avoid setting any -mXX flag on Itanium.

>> * The other issue concerns selecting a maximum SSE level. Right now I
>>can pick some Arch, but the SSE level up to SSE3 (==PNI) is determined
>>by the probes. So even if I pick a PIII for example I end up with SSE3
>>>support if the CPU supplies it. So far the trick I am using is to have
>>the SSE probe unconditionally return "FAILURE", so that for example I
>>get a SSE2 only ATLAS on a CPU with SSE3 or more. Obviously
>>performance will suck, but in case of Sage it is between "illegal
>>instructions" and working binaries, so performance  is something I can
>>sacrifice for that.
>>
>>Is there a plan to make the SSE level selectable as a config option?
>
> Not only is there a plan, but it's been available since 3.8.0!  It's not
> the easiest thing to grok, because one machine obviously can support many
> vector extensions.  Here is the line from 'configure --help':
>   -V #    # = ((1<<vecISA1) | (1<<vecISA2) | ... | (1<<vecISAN))

Ahh, I grepped around and found the enum ISAEXT, but I did not connect
the dots here after staring at the help output of configure for a
while.

> Now, since xprint_enums for some reason doens't print these values out,
> I can oh so conveniently scope ATLAS/CONFIG/include/atlconf.h for:
>   enum ISAEXT {ISA_None=0, ISA_AV, ISA_SSE3, ISA_SSE2, ISA_SSE1, ISA_3DNow};
>
> Therefore, if I want no vector code at all, I throw '-V -0'; if I want
> SSE2 & 1 but not 3, I throw (1<<3)+(1<<4) = 8+16=24, so '-V 24', and
> bingo: no SSE3 even on a machine that does SSE3!

Cool, I will be giving this a try.

> Cheers,
> Clint

Cheers,

Michael

> **************************************************************************
> ** R. Clint Whaley, PhD ** Assist Prof, UTSA ** www.cs.utsa.edu/~whaley **
> **************************************************************************
>
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