Re: Harvard caches

Hi,

Please, see my answer below. In MCF5407, there are 4 ACRx registers.
ACR0 and ACR1 are for data cache.
ACR2 and ACR3 are for instruction cache

If you initialise ACR0 and ACR1 with the same value, data and
instruction caches cover the same address range.

Here is the code I use to initialise cache :
    // Invalidate the cache and disable it
    SetMCF5407CACR (MCF5407_CACR_DCINVA);
    SetMCF5407CACR (MCF5407_CACR_BCINVA);
    SetMCF5407CACR (MCF5407_CACR_ICINVA);
    SetMCF5407CACR (MCF5407_CACR_DCINVA    |
                    MCF5407_CACR_BCINVA |
                    MCF5407_CACR_ICINVA    );//|
                    //MCF5407_CACR_HSDIS);
                           
    // Setup ACRs so that if cache is turned on, only SDRAM and Flash
are cached
    SetMCF5407ACR0 (MCF5407_ACR_BASE((INT32U)__SDRAM_START) |
//                    MCF5407_ACR_MASK(0x00FFFFFF) |      // 16Mo
//                    MCF5407_ACR_MASK(0x01FFFFFF) |      // 32Mo
                    MCF5407_ACR_MASK(0x03FFFFFF) |      // 64Mo
//                    MCF5407_ACR_MASK(0x07FFFFFF) |      // 128Mo
//                    MCF5407_ACR_MASK((INT32U)__HEAP_END -
(INT32U)__SDRAM_START) |  // See size in link file
                    MCF5407_ACR_E          |
//                    MCF5407_ACR_CM(0)      |        // Write-through
                    MCF5407_ACR_CM(1)      |        // Copyback
                    MCF5407_ACR_S(2));
                     
    SetMCF5407ACR1 (0);

    SetMCF5407ACR2 (MCF5407_ACR_BASE((INT32U)__FLASH_START) |
                    MCF5407_ACR_MASK(0x00) |
                    MCF5407_ACR_E          |
                    MCF5407_ACR_CM(0)      |
                    MCF5407_ACR_S(2));

    SetMCF5407ACR3 (0x00FFC060);            // See errata

    // Enable and configure cache
    SetMCF5407CACR (
                    MCF5407_CACR_DEC      |
                    MCF5407_CACR_DESB     |
                    MCF5407_CACR_DDCM (2) |
                    MCF5407_CACR_BEC      |
                    //MCF5407_CACR_HSDIS    |
                    MCF5407_CACR_IEC      |
                    MCF5407_CACR_DNFB     //|
////                    MCF5407_CACR_IDCM
                    );

In my case, data cache covers only SDRAM space and instruction cache
cover full address space (ACR MASK is 0).
If you want instruction and data cache to cover the same address range,
set ACR0 and ACR2 with the same value.
Note : SetMCF5407ACRx() and other functions are custom made functions
very dependent on the compiler.
>
> Another thing I don't understand is the two 4K SRAMs. The manual says
> I need to specifiy whether they are connected to the instruction bus
> or the data bus,. but it also gives RAMBAR address space settings for
> both code and data. Can I mix code and data in these RAMS, and if so,
> which bus do I specify and how does it work if they are one the wrong
> bus for the access?
>
MCF5407 has 2 internal RAM blocks. 4K each. There are 2 RAMBAR registers
(RAMBAR0 and RAMBAR1), one for each internal RAM block.
Each internal RAM block can be independently mapped anywhere in address
space modulo granularity trough RAMBARx.
An internal RAM block can be connected either on instruction bus or on
data bus NOT both.
That is, an internal RAM block can be used either for code or for data
NOT both.
If you configure an internal RAM block for data and you try to run code
from it, you will get an exception. Same thing with an internal RAM
block configure for instruction and accessed for data.


Hope this helps.

Regards,
Nicolas

> TIA, Chris
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