Re: Harvard caches

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nop head wrote:

I am moving some code from a MCF537x coldfire, which had a unified cache, to a MCF547x which has separate instruction and data caches.

My code has lots of tables declared as const so that they go into the read only text section in flash, rather than the initialised data section in RAM. Does this mean that all my table accesses will miss the cache because they will be in the range for the instruction cache, but are not instruction fetches?

Your table data will be read as data, and thus go in the data cache. The same applies to any other constant data that is generated along with the code (such as const values, strings, etc.).  Normally you would have your instruction cache range covering either all memory (probably the easiest), or all memory that can contain instructions.  Your data cache range should cover all memory except perhaps peripheral areas.

Similarly I have a few instructions in my bss section, mainly jump instruction to redirect interrupts to the relevent device driver. Am I right in thinking that these will all be cache misses as well because they will be in the range of the data cache but are actually instruction fetches?

Self-modifying code has been considered bad style for several decades. I don't know your particular code or the problem you are trying to solve, but as general advice you should try to use function pointers rather than jump instructions in your table.

If you want to keep the jump instructions, your main problem is cache synchronisation (ranges should be fixed as I said above).  When you change one of these indirect jumps, that's a data write and the change goes to the data cache.  The instruction cache knows nothing about the change (they are not synchronised - synchronising costs a lot of logic and latency).  You have to flush the relevant line of the data cache to make sure the change is written out, then you must flush the matching line in the instruction cache to make sure that you don't have old values in the instruction cache.  As you can see, using pointers is much easier.

Is there any way I can set up the caches to emulate a unified cache or do I have to rewrite all my code?

Another thing I don't understand is the two 4K SRAMs. The manual says I need to specifiy whether they are connected to the instruction bus or the data bus,. but it also gives RAMBAR address space settings for both code and data. Can I mix code and data in these RAMS, and if so, which bus do I specify and how does it work if they are one the wrong bus for the access?

TIA, Chris

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