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Re: I2C core VHDL testbench
by Mostafa-3
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Hi Richard,
Thanks for the clarification. Perhaps you could add this information
as a footnote in the docs or source preamble?
As 'H' is a valid VHDL logic level, I initially did not consider it a
problem -- resulting in time lost looking elsewhere =/
Best regards,
Mostafa
----- Original Message -----
From: Richard Herveille<richard@h...>
To:
Date: Thu Apr 19 21:40:38 CEST 2007
Subject: [oc] I2C core VHDL testbench
> Hi,
>
> There has been some previous debate regarding the 'H' versus '1' in
> VHDL.
> Consensus then was that an 'H' (weak/pull up high) inside a chip is
> a weird
> value.
> The pad or testbench should really convert 'H' into '1'.
> Richard
> -----Original Message-----
> From: cores-bounces at opencores.org [mailto:cores-bounces at
> opencores.org] On
> Behalf Of m.afgani at gmail.com
> Sent: Friday, April 20, 2007 12:17 AM
> To: cores at opencores.org
> Subject: Re: [oc] I2C core VHDL testbench
> Hello,
> I've finally succeeded in creating a simple WISHBONE master and
> testbench in VHDL that seems to work with the VHDL I2C core (ISE
> Sim
> 9.1.03i). One major issue appears to be the fact the core cannot
> deal
> with SCL/SDA lines that toggle between 'H' and '0' -- requiring the
> use of the /to_X01()/ function for /scl_i/ and /sda_i/ in the
> testbench. Also, I chose to use a VHDL model for a 24Cxx I2C EEPROM
> rather than the verilog slave model in CVS. An archive with the
> contributed files can be found here:
> http://m.afgani.googlepages.com/wb_i2c_tb.zip
> I started working on this project a few weeks ago with no prior
> knowledge of any HDL. Therefore, the code is certain to be lacking
> in
> many respects. I would really appreciate it if some of the more
> experienced users would have a look and provide some feedback.
> Many thanks to Richard for the core.
> Regards,
> Mostafa
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
Thanks for the clarification. Perhaps you could add this information
as a footnote in the docs or source preamble?
As 'H' is a valid VHDL logic level, I initially did not consider it a
problem -- resulting in time lost looking elsewhere =/
Best regards,
Mostafa
----- Original Message -----
From: Richard Herveille<richard@h...>
To:
Date: Thu Apr 19 21:40:38 CEST 2007
Subject: [oc] I2C core VHDL testbench
> Hi,
>
> There has been some previous debate regarding the 'H' versus '1' in
> VHDL.
> Consensus then was that an 'H' (weak/pull up high) inside a chip is
> a weird
> value.
> The pad or testbench should really convert 'H' into '1'.
> Richard
> -----Original Message-----
> From: cores-bounces at opencores.org [mailto:cores-bounces at
> opencores.org] On
> Behalf Of m.afgani at gmail.com
> Sent: Friday, April 20, 2007 12:17 AM
> To: cores at opencores.org
> Subject: Re: [oc] I2C core VHDL testbench
> Hello,
> I've finally succeeded in creating a simple WISHBONE master and
> testbench in VHDL that seems to work with the VHDL I2C core (ISE
> Sim
> 9.1.03i). One major issue appears to be the fact the core cannot
> deal
> with SCL/SDA lines that toggle between 'H' and '0' -- requiring the
> use of the /to_X01()/ function for /scl_i/ and /sda_i/ in the
> testbench. Also, I chose to use a VHDL model for a 24Cxx I2C EEPROM
> rather than the verilog slave model in CVS. An archive with the
> contributed files can be found here:
> http://m.afgani.googlepages.com/wb_i2c_tb.zip
> I started working on this project a few weeks ago with no prior
> knowledge of any HDL. Therefore, the code is certain to be lacking
> in
> many respects. I would really appreciate it if some of the more
> experienced users would have a look and provide some feedback.
> Many thanks to Richard for the core.
> Regards,
> Mostafa
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>
http://www.opencores.org/mailman/listinfo/cores
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