Hi,
The verilog testbench works for me. That's why it's all the more frustrating. I am using
Xilinx ISE 9.1.03i
Best,
Mostafa
PS> I'm copying this conversation to the OC forum
On 4/2/07, D R <
heedaf@...> wrote:
>
> I've been trying to get either verilog or vhdl versions to work. I'm trying to the
> verilog test bench to work but I'm getting similar errors. What software are you
> using? I'm thinking that unless you use synopsis it won't work.
----- Original Message -----
From: m.afgani at gmail.com<m.afgani@g...>
To:
Date: Mon Apr 2 02:18:49 CEST 2007
Subject: [oc] I2C core VHDL testbench
> Hello,
>
> I am trying to get a VHDL testbench running with the VHDL I2C core
> and
> and Verilog I2C slave model. I've implemented the WISHBONE master
> as a
> simple state machine. I tried to follow the same steps in the
> Verilog
> testbench in CVS but somehow that is insufficient. The I2C master
> drives the SCL and SDA lines from 'H' to '0' and '0' to 'H' as
> expected but the slave does not appear to respond to the commands.
> The
> slave SDA line is perpetually at 'Z'.
> At this point I am really not sure what might be wrong and am in
> desperate need of some help. The source files are available here:
>
http://m.afgani.googlepages.com/WB_I2C.zip
> Thanks in advance,
> Mostafa
>
>
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