Did you connect clock and data signals correctly? It is a bit tricky
because you don't use the clock and data out lines for the actual data
transfer. They are always 0.
You have to use the data and output enable to make 1 and 0.
Hope it is of help.
Regands,
David
----- Original Message -----
From: froger.e0300617 at
etud.univ-ubs.fr<froger.e0300617@e...>
To:
Date: Tue Jan 24 20:24:08 CET 2006
Subject: [oc] I2C ip core integration for ALTERA FPGAs
> I have the same probleme than you. I can't write in the register .
> For
> presc_HI, it is OK but for the other register, it 's always NULL.
> Does somebody has t this I2C master's driver files?
> thank you
> Arnaud
> ----- Original Message -----
> From: zhangming98 at hotmail.com<zhangming98 at h...>
> To:
> Date: Wed Aug 3 06:40:08 CEST 2005
> Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > Hi, Richard, Thanks for your remind, I am going to code it...
> > However, the core seems not working. It is no response to my
> IOWR
> > (i2c_base, 0x00, 0x63) and IOWR(i2c_base, 0x01,0x00). The
> result of
> > reading the 2 regs after above action is still 0xff each. I
> > connected the
> > signals to Avalon Slave port according to deep below of this
> email
> > and
> > SCL/SDA were also instantiated..
> > Kindly please advise me.
> > R.G
> > Ming
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