Re: I2C ip core integration for ALTERA FPGAs

[froger.e0300617]

I have the same probleme than you. I can't write in the register . For
presc_HI, it is OK but for the other register, it 's always NULL.

Does somebody has t this I2C master's driver files?

thank you

Arnaud
----- Original Message -----
From: zhangming98 at hotmail.com<zhangming98@h...>
To:
Date: Wed Aug  3 06:40:08 CEST 2005
Subject: [oc] I2C ip core integration for ALTERA FPGAs

> Hi, Richard, Thanks for your remind, I am going to code it...
> However, the core seems not working. It is no response to my IOWR
> (i2c_base, 0x00, 0x63) and IOWR(i2c_base, 0x01,0x00). The result of
> reading the 2 regs after above action is still 0xff each. I
> connected the
> signals to Avalon Slave port according to deep below of this email
> and
> SCL/SDA were also instantiated..
> Kindly please advise me.
> R.G
> Ming
> ----- Original Message -----
> From: Richard Herveille<richard at h...>
> To:
> Date: Thu Jul 28 15:46:36 CEST 2005
> Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > As in device drivers??
> > You have to code them yourself.
> > Richard
> > -----Original Message-----
> > From: cores-bounces at opencores.org [mailto:cores-bounces at
> > opencores.org] On
> > Behalf Of zhangming98 at hotmail.com
> > Sent: Monday, July 25, 2005 5:59 PM
> > To: cores at opencores.org
> > Subject: Re: [oc] I2C ip core integration for ALTERA FPGAs
> > Hi, Richard,
> > Would you please post this I2C master's driver files? It is a
> hard
> > time for
> > me to code it for Altera NiosII since I am totally new to the
> > platform.
> > Thanks a lot!
> > Ming
> > ----- Original Message -----
> > From: Richard Herveille<richard at h...>
> > To:
> > Date: Thu Jan 27 18:16:52 CET 2005
> > Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > > What do you mean when you say you don't get a response?
> > > Can you check that your writing into the regs correctly
> (check
> > CYC,
> > > STB).
> > > The core should respond with an ACK.
> > > Now if you're checking the scl and sda signals, make sure
> you
> > > hooked up the
> > > tri-state output correctly and you pulled-up the wires.
> > > Otherwise the core won't work.
> > > Cheers,
> > > Richard
> > >
> > > > -----Original Message-----
> > > > From: cores-bounces at o...
> > > > [mailto:cores-bounces at o...] On Behalf Of
> > > > David2565 at h...
> > > > Sent: Friday, January 21, 2005 4:34 PM
> > > > To: cores at o...
> > > > Subject: Re: [oc] I2C ip core integration for ALTERA
> > FPGAs
> > > >
> > > > Hi,
> > > >
> > > > I tried to use this I2C core(the VHDL version) in a
> NIOS2
> > > > system with quartus 2(4.1) I connected everything
> like
> > stated
> > > > below, but I get no response from it when I write to
> a
> > > register.
> > > > I did not connect the other end of the I2C chanel
> because
> > I
> > > > want to make sure it was connected properly. Could
> that
> > be
> > > > the problem?
> > > >
> > > > I used the following commands to try to send
> something:
> > > > [code]
> > > >
> IOWR_8DIRECT(I2C_BASE,OC_I2C_CR,IORD_8DIRECT(I2C_BASE,
> > > > OC_I2C_CR)|OC_I2C_EN); //chip enable
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_PRER_LO,0x50);//set
> > prescaler
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_PRER_HI,0x00);
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_TXR,0xAC);// set write
> adres
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_SR,(IORD_8DIRECT
> > > > (I2C_BASE,OC_I2C_SR)|OC_I2C_STA|OC_I2C_WR));//set
> some
> > other
> > > > bits
> > >
> printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR));//
> > check
> > > (i get
> > > > FF!?)
> > > > while(IORD_8DIRECT(I2C_BASE,OC_I2C_SR)&
> OC_I2C_TIP);
> > > >
> > printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR));
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_TXR,0x5C);
> > > >
> > printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR));
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_SR,(IORD_8DIRECT
> > > > (I2C_BASE,OC_I2C_SR)|OC_I2C_STO|OC_I2C_WR));
> > > > [/code]
> > > >
> > > > Hope someone can help,
> > > > David > > > > > > > > >
> ----- Original Message ----- > > > From: c.scherp at
> 3...<c.scherp at 3...> > > > To: > > >
> Date: Thu Apr 15 16:20:50 CEST 2004 > > > Subject: [oc]
> I2C ip core integration for ALTERA FPGAs > > > > >
> > > Hallo Guido, > > > > > > > > it
> works ! Thank you very much for helping me ! > > > >
> > > > > Christian. > > > > > > >
> > Datum: Fri, 2 Apr 2004 14:22:33 +0200 > > > >
> Von: "Guido Kuhlmann" > > > >
> <Guido.Kuhlmann at t...> > > > > Betreff: RE:
> [oc] I2C ip core integration for > > > > ALTERA FPGAs
> > > > > An: "'Discussion list about free open
> source > IP > > > > cores'" <cores at
> o...> > > > > Antwort an: Guido.Kuhlmann at t...,
> > > > Discussion > list about free open source IP
> cores > <cores at o...> [ > > > > Doppelklick
> auf diese Zeile zeigt Optionen für > > Abo-Liste ] Hi
> > > > Christian, you can easily > connect the I2C
> Wishbone core > to the NIOS > > > > processor (I
> don't know the simple I2C core). > > > 1. > Within SOPC
> builder, generate interface to user logic. > > > > 2.
> Select bus interface type: avalon register slave. > > >
> > 3. Add "i2c_master_top.v" design file. > >
> > > 4. Read port list from file. > > > 5. Connect
> the > signals as follow: > > > wb_adr_i <=>
> address > > > > wb_dat_i <=> writedata > >
> > wb_dat_o > <=> readdata > > > wb_we_i
> <=> write > > > > wb_stb_i <=> chipselect
> > > > wb_cyc_i > <=> chipselect > > >
> wb_inta_o <=> irq > > > > wb_clk_i <=> clk
> > > > wb_ack_o <=> > waitrequest_n > > >
> wb_rst_i <=> always0 > > > > arst_i <=>
> reset_n > > > scl_pad_i <=> > export > >
> > scl_pad_o <=> export > > > > scl_padoen_o
> <=> export > > > sda_pad_i <=> > export
> > > > sda_pad_o <=> export > > > >
> sda_padoen_o <=> export > > > 6. Under timing tab,
> > leave the setup, wait and hold > settings at 0 > >
> > > cycles. > > You can now access the I2C core via
> > included > "oc_i2c_master.h". > > Hope this
> helps. > > > > Guido. > > > >
> ______________________________________________________ > >
> > > _______ > > Guido Kuhlmann > > Tigris
> Elektronik > GmbH > http://www.tigris.de > > > >
> ______________________________________________________ > >
> > > _______ > > > -----Original Message----- >
> > > > > From: cores-bounces at o... > > > >
> > [mailto:cores-bounces at o...]On > > > Behalf Of >
> > c.scherp at 3... > > > Sent: Wednesday, March 31,
> 2004 > 10:31 > AM > > > To: cores at o... > >
> > > Subject: [oc] I2C > ip core integration for ALTERA
> FPGAs > > > > > > > > > > > >
> > > > I´m new to opencores.org and I > want to
> integrate a simple > > > I2C > > > Bus Master
> > Interface > > > > in an ALTERA Apex / Cyclone /
> Stratix > Device with > > QuartusII and SOPC > >
> > Builder. I do > not need the > complex wishbone version
> of > the I2C core. > > > > I´m > > >
> happy with the simple > > > > > I2C Bus Master which
> can be found in I2C.vhd. Is there any > > > > >
> documentation available for this version ? Or can > anyone >
> > give some > > > advice how to connect > this core
> to > the ALTERA Avalon Bus and the > > > > ALTERA
> Nios > Soft-Processor ? Thank > > you... > > >
> > Christian. > > > > > > > > > >
> > > > > >
> _______________________________________________ > > > >
> > http://www.opencores.org/mailman/listinfo/cores > > >
> > > > > >
> _______________________________________________ > > > >
> http://www.opencores.org/mailman/listinfo/cores > > -- >
> > > > 3D Alliance GmbH > > Hauptstr. 46 > >
> 35649 > > Bischoffen > > Tel. 06444 / 93 19 - 0 Fax.
> 06444 / 93 19 > - 12 > > > > >
> _______________________________________________ > > >
> http://www.opencores.org/mailman/listinfo/cores > > >
> _______________________________________________ >
> http://www.opencores.org/mailman/listinfo/cores >
>

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Mark McDougall]

froger.e0300617@... wrote:

> I have the same probleme than you. I can't write in the register .
> For presc_HI, it is OK but for the other register, it 's always NULL.

I recently sucessfully integrated the I2C core onto an Avalon bus in a
Cyclone II without any problems whatsoever.

I used a top-level wrapper to convert the unsigned wb_adr_i to
std_logic_vector and also remove the std_logic generic ARST_LVL (SOPC
Builder barfs on std_logic parameters).

I guess the only difference here is that I'm not actually talking to it
from the NIOS, but rather from another micro which interfaces to the
Avalon bus externally.

But I can confirm that it does indeed work.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: [phone] Fax: [phone]

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Norman McCall]

Microtronix has taken the OC I2C component and developed a I2C
Design Kit with a Santa Cruz development board.  The product provides
an Altera SOPC component, reference designs for most Altera boards,
uClinux Master drivers and sample applications.  A HAL component will
be available in the next release.

If you want to save design time check it out here:  
http://www.microtronix.com/product_i2c.html

Norm

----- Original Message -----
From: froger.e0300617 at
etud.univ-ubs.fr<froger.e0300617@e...>
To:
Date: Tue Jan 24 20:24:08 CET 2006
Subject: [oc] I2C ip core integration for ALTERA FPGAs

> I have the same probleme than you. I can't write in the register .
> For
> presc_HI, it is OK but for the other register, it 's always NULL.
> Does somebody has t this I2C master's driver files?
> thank you
> Arnaud
> ----- Original Message -----
> From: zhangming98 at hotmail.com<zhangming98 at h...>
> To:
> Date: Wed Aug 3 06:40:08 CEST 2005
> Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > Hi, Richard, Thanks for your remind, I am going to code it...
> > However, the core seems not working. It is no response to my
> IOWR
> > (i2c_base, 0x00, 0x63) and IOWR(i2c_base, 0x01,0x00). The
> result of
> > reading the 2 regs after above action is still 0xff each. I
> > connected the
> > signals to Avalon Slave port according to deep below of this
> email
> > and
> > SCL/SDA were also instantiated..
> > Kindly please advise me.
> > R.G
> > Ming
> > ----- Original Message -----
> > From: Richard Herveille<richard at h...>
> > To:
> > Date: Thu Jul 28 15:46:36 CEST 2005
> > Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > > As in device drivers??
> > > You have to code them yourself.
> > > Richard
> > > -----Original Message-----
> > > From: cores-bounces at opencores.org
> [mailto:cores-bounces at
> > > opencores.org] On
> > > Behalf Of zhangming98 at hotmail.com
> > > Sent: Monday, July 25, 2005 5:59 PM
> > > To: cores at opencores.org
> > > Subject: Re: [oc] I2C ip core integration for ALTERA
> FPGAs
> > > Hi, Richard,
> > > Would you please post this I2C master's driver files? It
> is a
> > hard
> > > time for
> > > me to code it for Altera NiosII since I am totally new to
> the
> > > platform.
> > > Thanks a lot!
> > > Ming
> > > ----- Original Message -----
> > > From: Richard Herveille<richard at h...>
> > > To:
> > > Date: Thu Jan 27 18:16:52 CET 2005
> > > Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > > > What do you mean when you say you don't get a
> response?
> > > > Can you check that your writing into the regs
> correctly
> > (check
> > > CYC,
> > > > STB).
> > > > The core should respond with an ACK.
> > > > Now if you're checking the scl and sda signals, make
> sure
> > you
> > > > hooked up the
> > > > tri-state output correctly and you pulled-up the
> wires.
> > > > Otherwise the core won't work.
> > > > Cheers,
> > > > Richard
> > > >
> > > > > -----Original Message-----
> > > > > From: cores-bounces at o...
> > > > > [mailto:cores-bounces at o...] On Behalf Of
> > > > > David2565 at h...
> > > > > Sent: Friday, January 21, 2005 4:34 PM
> > > > > To: cores at o...
> > > > > Subject: Re: [oc] I2C ip core integration for
> ALTERA
> > > FPGAs
> > > > >
> > > > > Hi,
> > > > >
> > > > > I tried to use this I2C core(the VHDL version)
> in a
> > NIOS2
> > > > > system with quartus 2(4.1) I connected
> everything
> > like
> > > stated
> > > > > below, but I get no response from it when I
> write to
> > a
> > > > register.
> > > > > I did not connect the other end of the I2C
> chanel
> > because
> > > I
> > > > > want to make sure it was connected properly.
> Could
> > that
> > > be
> > > > > the problem?
> > > > >
> > > > > I used the following commands to try to send
> > something:
> > > > > [code]
> > > > >
> > IOWR_8DIRECT(I2C_BASE,OC_I2C_CR,IORD_8DIRECT(I2C_BASE,
> > > > > OC_I2C_CR)|OC_I2C_EN); //chip enable
> > > > >
> IOWR_8DIRECT(I2C_BASE,OC_I2C_PRER_LO,0x50);//set > >
> prescaler > > > >
> IOWR_8DIRECT(I2C_BASE,OC_I2C_PRER_HI,0x00); > > > >
> IOWR_8DIRECT(I2C_BASE,OC_I2C_TXR,0xAC);// set write > adres >
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_SR,(IORD_8DIRECT >
> > > > (I2C_BASE,OC_I2C_SR)|OC_I2C_STA|OC_I2C_WR));//set
> > some > > other > > > > bits > > >
> > printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR));//
> > > check > > > (i get > > > > FF!?)
> > > > > while(IORD_8DIRECT(I2C_BASE,OC_I2C_SR)&
> > OC_I2C_TIP); > > > > > >
> printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR)); >
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_TXR,0x5C); > >
> > > > >
> printf("%x\n",IORD_8DIRECT(I2C_BASE,OC_I2C_SR)); >
> > > > IOWR_8DIRECT(I2C_BASE,OC_I2C_SR,(IORD_8DIRECT >
> > > > (I2C_BASE,OC_I2C_SR)|OC_I2C_STO|OC_I2C_WR)); >
> > > > [/code] > > > > > > > > Hope
> someone can help, > > > > David > > > >
> > > > > > > ----- Original Message ----- >
> > > From: c.scherp at > 3...<c.scherp at 3...> >
> > > To: > > > > Date: Thu Apr 15 16:20:50 CEST
> 2004 > > > Subject: [oc] > I2C ip core integration for
> ALTERA FPGAs > > > > > > > > Hallo Guido,
> > > > > > > > > it > works ! Thank you
> very much for helping me ! > > > > > > > >
> > Christian. > > > > > > > > > Datum:
> Fri, 2 Apr 2004 14:22:33 +0200 > > > > > Von:
> "Guido Kuhlmann" > > > > >
> <Guido.Kuhlmann at t...> > > > > Betreff: RE:
> > [oc] I2C ip core integration for > > > > ALTERA
> FPGAs > > > > > An: "'Discussion list about
> free open > source > IP > > > > cores'"
> <cores at > o...> > > > > Antwort an:
> Guido.Kuhlmann at t..., > > > > Discussion > list
> about free open source IP > cores > <cores at o...> [
> > > > > Doppelklick > auf diese Zeile zeigt Optionen
> für > > Abo-Liste ] Hi > > > > Christian,
> you can easily > connect the I2C > Wishbone core > to the
> NIOS > > > > processor (I > don't know the simple
> I2C core). > > > 1. > Within SOPC > builder,
> generate interface to user logic. > > > > 2. >
> Select bus interface type: avalon register slave. > > >
> > > 3. Add "i2c_master_top.v" design file. >
> > > > > 4. Read port list from file. > > > 5.
> Connect > the > signals as follow: > > > wb_adr_i
> <=> > address > > > > wb_dat_i <=>
> writedata > > > > wb_dat_o > <=> readdata >
> > > wb_we_i > <=> write > > > > wb_stb_i
> <=> chipselect > > > > wb_cyc_i > <=>
> chipselect > > > > wb_inta_o <=> irq > >
> > > wb_clk_i <=> clk > > > > wb_ack_o
> <=> > waitrequest_n > > > > wb_rst_i <=>
> always0 > > > > arst_i <=> > reset_n > >
> > scl_pad_i <=> > export > > > > scl_pad_o
> <=> export > > > > scl_padoen_o > <=>
> export > > > sda_pad_i <=> > export > >
> > > sda_pad_o <=> export > > > > >
> sda_padoen_o <=> export > > > 6. Under timing tab,
> > > leave the setup, wait and hold > settings at 0 >
> > > > > cycles. > > You can now access the I2C
> core via > > included > "oc_i2c_master.h". >
> > Hope this > helps. > > > > Guido. > >
> > > >
> ______________________________________________________ > >
> > > > _______ > > Guido Kuhlmann > > Tigris
> > Elektronik > GmbH > http://www.tigris.de > > >
> > > ______________________________________________________
> > > > > > _______ > > > -----Original
> Message----- > > > > > > From: cores-bounces at
> o... > > > > > > [mailto:cores-bounces at o...]On
> > > > Behalf Of > > > c.scherp at 3... > >
> > Sent: Wednesday, March 31, > 2004 > 10:31 > AM >
> > > To: cores at o... > > > > > Subject: [oc]
> I2C > ip core integration for ALTERA > FPGAs > > >
> > > > > > > > > > > > > >
> I´m new to opencores.org and I > want to > integrate a
> simple > > > I2C > > > Bus Master > >
> Interface > > > > in an ALTERA Apex / Cyclone / >
> Stratix > Device with > > QuartusII and SOPC > >
> > > Builder. I do > not need the > complex wishbone
> version > of > the I2C core. > > > > I´m
> > > > > happy with the simple > > > > >
> I2C Bus Master which > can be found in I2C.vhd. Is there any
> > > > > > > documentation available for this
> version ? Or can > anyone > > > give some > >
> > advice how to connect > this core > to > the ALTERA
> Avalon Bus and the > > > > ALTERA > Nios >
> Soft-Processor ? Thank > > you... > > > > >
> Christian. > > > > > > > > > > >
> > > > > > >
> _______________________________________________ > > > >
> > > http://www.opencores.org/mailman/listinfo/cores > >
> > > > > > > > >
> _______________________________________________ > > > >
> > http://www.opencores.org/mailman/listinfo/cores > > --
> > > > > > 3D Alliance GmbH > > Hauptstr. 46
> > > > 35649 > > Bischoffen > > Tel. 06444 / 93
> 19 - 0 Fax. > 06444 / 93 19 > - 12 > > > > >
> > _______________________________________________ > > >
> > http://www.opencores.org/mailman/listinfo/cores > > >
> > _______________________________________________ > >
> http://www.opencores.org/mailman/listinfo/cores > >
>

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Richard Herveille]

Hi Mark,

Are you willing to share the wrapper?
I can add it to the tarball.
More people are asking for this ...


Thanks,
Richard


-----Original Message-----
From: cores-bounces@... [mailto:cores-bounces@...] On
Behalf Of Mark McDougall
Sent: Friday, January 27, 2006 12:21 AM
To: Discussion list about free open source IP cores
Subject: Re: [oc] I2C ip core integration for ALTERA FPGAs

froger.e0300617@... wrote:

> I have the same probleme than you. I can't write in the register .
> For presc_HI, it is OK but for the other register, it 's always NULL.

I recently sucessfully integrated the I2C core onto an Avalon bus in a
Cyclone II without any problems whatsoever.

I used a top-level wrapper to convert the unsigned wb_adr_i to
std_logic_vector and also remove the std_logic generic ARST_LVL (SOPC
Builder barfs on std_logic parameters).

I guess the only difference here is that I'm not actually talking to it
from the NIOS, but rather from another micro which interfaces to the
Avalon bus externally.

But I can confirm that it does indeed work.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: [phone] Fax: [phone]

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[David.Wessels]

Did you connect clock and data signals correctly? It is a bit tricky
because you don't use the clock and data out lines for the actual data
transfer. They are always 0.
You have to use the data and output enable to make 1 and 0.

Hope it is of help.
Regands,
David

----- Original Message -----
From: froger.e0300617 at
etud.univ-ubs.fr<froger.e0300617@e...>
To:
Date: Tue Jan 24 20:24:08 CET 2006
Subject: [oc] I2C ip core integration for ALTERA FPGAs

> I have the same probleme than you. I can't write in the register .
> For
> presc_HI, it is OK but for the other register, it 's always NULL.
> Does somebody has t this I2C master's driver files?
> thank you
> Arnaud
> ----- Original Message -----
> From: zhangming98 at hotmail.com<zhangming98 at h...>
> To:
> Date: Wed Aug 3 06:40:08 CEST 2005
> Subject: [oc] I2C ip core integration for ALTERA FPGAs
> > Hi, Richard, Thanks for your remind, I am going to code it...
> > However, the core seems not working. It is no response to my
> IOWR
> > (i2c_base, 0x00, 0x63) and IOWR(i2c_base, 0x01,0x00). The
> result of
> > reading the 2 regs after above action is still 0xff each. I
> > connected the
> > signals to Avalon Slave port according to deep below of this
> email
> > and
> > SCL/SDA were also instantiated..
> > Kindly please advise me.
> > R.G
> > Ming

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[ferrarino]

Hello,
I have created the avalon bus as Guido told in this post.
I wanted to know if he used the wrapper to convert the address bus from
unisgned to standard logic vector.....or not?
If yes, I have no idea of how to do it....any suggestions?
After created the avalon bus, have I to use the oc_i2c_master.h function to
write and read the I2C?

thanks,
Giuseppe
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[ferrarino]

Hello,
I have created the avalon bus as Guido told in this post.
I wanted to know if he used the wrapper to convert the address bus from
unisgned to standard logic vector.....or not?
If yes, I have no idea of how to do it....any suggestions?
After created the avalon bus, have I to use the oc_i2c_master.h function to
write and read the I2C?

thanks,
Giuseppe
--
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[ferrarino]

ferrarino wrote:

>
> Hello,
> I have created the avalon bus as Guido told in this post.
> I wanted to know if he used the wrapper to convert the address bus from
> unisgned to standard logic vector.....or not?
> If yes, I have no idea of how to do it....any suggestions?
> After created the avalon bus, have I to use the oc_i2c_master.h function
> to write and read the I2C?
>
> thanks,
> Giuseppe
>

I tried to compile the project but without the wrapper there is an error: a
mismatching between the wb_adr_i of  the sopc (std_logic_vector) and the
I2C_master_top (unsigned). So I need this wrapper.......how do I create it?

thanks,
Giuseppe
--
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[ferrarino]

Hello,
I have created the avalon bus as Guido told in this post.
I tried to compile the project but there is an error: a mismatching between the wb_adr_i of  the sopc (std_logic_vector) and the I2C_master_top (unsigned). So I need this wrapper.......how do I create it?
Please tell me any suggestions!!!!
After created the avalon bus, have I to use the oc_i2c_master.h function to write and read the I2C?

thanks,
Giuseppe

[ferrarino]

I have been able to to the wrapper and link it to the avalon bus of NiosII.
Now I have the common problem that I'm not able to write in the registers except prescalere one.
What have I to do? P.s. the scl and sda line are pulled up with 4,7k resistors.(even if now I have done a weak pull-up directly on pins by Quartus)

Any suggestions?
Thanks,
Giuseppe

[Jose_Angel]

Hello, i am working in a equivalent vhdl code with intersil HD-6409
Manchester Encoder-Decoder, and i would be very interested in sharing or
collaborating if somebody knows or has worked previously in it.

Thanks for all.
_______________________________________________________

José Ángel Domínguez Mateos
Laboratorio de Optoelectrónica
Área de Cargas Útiles e Instrumentación
Departamento de Programas Espaciales y Ciencias del Espacio
Instituto Nacional de Técnica Aeroespacial - INTA
28850 Torrejon de Ardoz - Madrid - SPAIN

Tel. [phone] Fax. [phone] E-mail dominguezmja@...
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