Re: RE: DDR ram issue using MCF54450 @240Mhz

Hey Greg,

Its gerry here!  I'm sorry I have not been able to reply, but I'm still without power! (since thursday!). Blackberies for once are coming in handy!


That aside,  when I read your original email, I was going to suggest turning off cache, as that will inhibit bursting. 

So, one thing you want to make sure still lines up on your design is that the correct lines are connected to the bank pins on the dram.  If not, the commands that are sent to the sdram registers inside of the sdram chip using the control lines will not be decoded correctly.  For example, when the burst length gets sent.

Go through all the bootup code for sdram, and make sure you can see that the commands are matchung up with with the correct lines on the sdram.  There is usually a table in the sdram datasheet which shows what combinations of control lines make up which command.

Not saying this is it, as I know you used the same part as us, but itou did mention that you have it connected differently.



----- Original Message -----
From: coldfire-bounce@... <coldfire-bounce@...>
To: Vahe Gerald-B06319
Sent: Wed Dec 17 09:19:09 2008
Subject: [ColdFire] RE: DDR ram issue using MCF54450 @240Mhz

Hi all



More to report my actual problem appears to be cache I have disabled icache and u-boot seems to be working as expected. If I type (icache on) the system locks up. Anyone know if this symptom is telling me something I need to look at such a layout other variables ect.



Gregg



________________________________

Gregg GRANVILLE

Hardware Engineering Manager

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Tel 1 603.622.0212 / Fax 1 603.623.5623

ggranville@... <ggranville@...>  / www.metronics.com <http://www.metronics.com>

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METRONICS /// 30 Harvey Road // Bedford, NH 03110-6818 / US

From: coldfire-bounce@... [coldfire-bounce@...] On Behalf Of Granville Gregg
Sent: Wednesday, December 17, 2008 8:00 AM
To: Granville Gregg
Subject: [ColdFire] DDR ram issue using MCF54450 @240Mhz



We have a MCF54450 running at a CPU CLK of 240Mhz. we are using U-Boot  1.2.0 our design is using 1 16 bit Flash a PC28F256P33B85 BGA64. We are executing code in Flash and have written a DDR-ram test walking ones and walking zeros and address and address this will run for days at a time billions and billions of writes and reads.

When we move this to DDR-ram which is a MICRON MT47H64M8CF-3:F which we use two of on SD-16 through SD-31with SD_A0-SD_A13 and

SD_CS

SD_DM2

SD_DQS2

SD_DM3

SD_DMQS3



We cannot run code we are using the same settings as the Reference design the same chips. I have layed out the board with mentor and have put restraints in all of the lines to keep them within .4 inches in length.



The symptoms are it either gets an exception out in space or locks up before it gets to NET: functions



Anyone have any thoughts about the issue.



Gregg





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