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Re: RE: DDR ram issue using MCF54450 @240Mhz
by David Brown-4
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Granville Gregg wrote:
> Hi Gerry
>
>
>
> This how we have them connected the only difference from our board and
> the reference design is that we have two less chips. We removed the
> chips that were connected to the SD_CS1 our burst mode is set at both
> ends to 8 I have tried 4 as well but then the SDRAM will not even
> function. Maybe you could pass this along to someone else if you need to
> if you need the code as well let me know what file or files.
>
>
>
> Our basic problem is we cannot turn cache on and execute code with cache
> disabled everything works fine.
>
>
I don't know if this is of any help at all, but I had similar symptoms
with a MCF5235 and SDRAM - with the icache disabled, everything worked
fine, but enabling it caused crashes. It turned out to be an incorrect
setting in the CBM field of the DACR register (I presume the DDR
registers have similar names). I don't know quite why, but this caused
burst reads to fail for all addresses with A17 high (IIRC - it may have
been a different address line) - the first two reads in the burst were
correct but the others were always read as copies of the second word of
the burst read. What made this especially fun was that my test code
fitted within the first working block - it was the customer's code that
was large enough to be caught out.
I'd recommend double checking your DDR connections, the ColdFire
register setup, and the initialisation sequence. Then put all your
notes away and figure out the settings again from scratch.
mvh.,
David
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Granville Gregg wrote:
> Hi Gerry
>
>
>
> This how we have them connected the only difference from our board and
> the reference design is that we have two less chips. We removed the
> chips that were connected to the SD_CS1 our burst mode is set at both
> ends to 8 I have tried 4 as well but then the SDRAM will not even
> function. Maybe you could pass this along to someone else if you need to
> if you need the code as well let me know what file or files.
>
>
>
> Our basic problem is we cannot turn cache on and execute code with cache
> disabled everything works fine.
>
>
I don't know if this is of any help at all, but I had similar symptoms
with a MCF5235 and SDRAM - with the icache disabled, everything worked
fine, but enabling it caused crashes. It turned out to be an incorrect
setting in the CBM field of the DACR register (I presume the DDR
registers have similar names). I don't know quite why, but this caused
burst reads to fail for all addresses with A17 high (IIRC - it may have
been a different address line) - the first two reads in the burst were
correct but the others were always read as copies of the second word of
the burst read. What made this especially fun was that my test code
fitted within the first working block - it was the customer's code that
was large enough to be caught out.
I'd recommend double checking your DDR connections, the ColdFire
register setup, and the initialisation sequence. Then put all your
notes away and figure out the settings again from scratch.
mvh.,
David
---
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