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Re: contiguous DMA while transferring data over IP

by Eugene Grayver :: Rate this Message:

Hmm... I must be entirely ignorant about the details of PXA DMA transfers. We modified the kernel to have 16MB of coherent memory space and were doing a single LONG DMA transfer from the FIFO to the memory. I did not realize that the transfer was already being broken up into 8k chunks. I would be entirely happy with chunks of ~100kB. However, when I tried to break the transfer up into multiple DMAs from user mode, I got overruns.

----- Original Message ----
From: Ned Forrester <nforrester@...>
To: General mailing list for gumstix users. <gumstix-users@...>
Sent: Friday, June 26, 2009 9:01:06 PM
Subject: Re: [Gumstix-users] contiguous DMA while transferring data over IP

On 06/26/2009 11:01 PM, Eugene Grayver wrote:

> Hello,
>
> I am using a Verdex video interface to capture data from a custom CCD
> processor. The interface goes directly into a small FIFO on the
> PXA270. I setup a DMA to get data from the FIFO into bulk memory.
> After an image has been transferred, it is sent over the network to a
> server. It takes too long to capture the image and then send it out.
> I'd like to start sending data out while it is being received.
> Unfortunately, the DMA buffer is locked and cannot be accessed by the
> user-space program while DMA is running.
>
> My idea is to break up the transfer into N smaller DMAs. As each DMA
> completes, I transfer that chunk, while the next DMA is writing to a
> new buffer. The way the custom hardware is setup, I cannot tolerate
> pauses in emptying the FIFO (it will overrun). Thus, I need the DMAs
> to run (almost) contiguously. Is there a way to queue up all N DMA
> requests and have the kernel take care of starting each one after the
> previous one has completed?

Yes, but you will likely have to re-write the kernel driver to support
that. The PXA series has support for descriptor-fetch DMA, in which the
essential DMA registers are re-loaded from memory by the DMA hardware,
itself, so that DMA buffers can be filled one after another without
intervention by the CPU. I have used this successfully in a re-write of
pxa2xx_spi.c, which is the driver for the SPI interface.

The maximum DMA length in the PXA2xx processors is only 8191 bytes, so I
find it hard to believe that you would want the buffer length to be any
smaller (than possibly 4096 bytes) if you are transferring images.

--
Ned Forrester nforrester@...
Oceanographic Systems Lab 508-289-2226
Applied Ocean Physics and Engineering Dept.
Woods Hole Oceanographic Institution Woods Hole, MA 02543, USA
http://www.whoi.edu/
http://www.whoi.edu/sbl/liteSite.do?litesiteid=7212
http://www.whoi.edu/hpb/Site.do?id=1532
http://www.whoi.edu/page.do?pid=10079

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