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Re: contiguous DMA while transferring data over IP
by Ned Forrester
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On 06/30/2009 08:37 PM, Eugene Grayver wrote:
> Hmm... I must be entirely ignorant about the details of PXA DMA
> transfers. We modified the kernel to have 16MB of coherent memory
> space and were doing a single LONG DMA transfer from the FIFO to the
> memory. I did not realize that the transfer was already being broken
> up into 8k chunks. I would be entirely happy with chunks of ~100kB.
> However, when I tried to break the transfer up into multiple DMAs
> from user mode, I got overruns.
Hmmm... The kernel driver must be breaking the transfer into smaller
bits. I suggest you take a look at the driver code and see if you can
figure out what it is doing for you with regard to partitioning the DMA
and how it is managing to keep up with the data input. I gather 16MB is
enough for a whole picture.
Exactly which peripheral on the PXA270 are you using? Which driver?
What speed (bytes/sec) does this device require?
If you are using the Quick Capture Interface, I see reference in section
27.4.4.3 of the Developer's Manual to setting up a descriptor chain for
and entire frame. That is what I would expect to be required to capture
data from an external device that is supplying the transfer clock.
Perhaps this is what the kernel driver is doing.
Do you really have to get a single frame faster, or is it a matter of
keeping up with a particular frame rate? If the latter, could you just
use two buffers so that you can be transmitting one while the other is
being filled by the driver?
--
Ned Forrester nforrester@...
Oceanographic Systems Lab 508-289-2226
Applied Ocean Physics and Engineering Dept.
Woods Hole Oceanographic Institution Woods Hole, MA 02543, USA
http://www.whoi.edu/
http://www.whoi.edu/sbl/liteSite.do?litesiteid=7212
http://www.whoi.edu/hpb/Site.do?id=1532
http://www.whoi.edu/page.do?pid=10079
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> Hmm... I must be entirely ignorant about the details of PXA DMA
> transfers. We modified the kernel to have 16MB of coherent memory
> space and were doing a single LONG DMA transfer from the FIFO to the
> memory. I did not realize that the transfer was already being broken
> up into 8k chunks. I would be entirely happy with chunks of ~100kB.
> However, when I tried to break the transfer up into multiple DMAs
> from user mode, I got overruns.
Hmmm... The kernel driver must be breaking the transfer into smaller
bits. I suggest you take a look at the driver code and see if you can
figure out what it is doing for you with regard to partitioning the DMA
and how it is managing to keep up with the data input. I gather 16MB is
enough for a whole picture.
Exactly which peripheral on the PXA270 are you using? Which driver?
What speed (bytes/sec) does this device require?
If you are using the Quick Capture Interface, I see reference in section
27.4.4.3 of the Developer's Manual to setting up a descriptor chain for
and entire frame. That is what I would expect to be required to capture
data from an external device that is supplying the transfer clock.
Perhaps this is what the kernel driver is doing.
Do you really have to get a single frame faster, or is it a matter of
keeping up with a particular frame rate? If the latter, could you just
use two buffers so that you can be transmitting one while the other is
being filled by the driver?
--
Ned Forrester nforrester@...
Oceanographic Systems Lab 508-289-2226
Applied Ocean Physics and Engineering Dept.
Woods Hole Oceanographic Institution Woods Hole, MA 02543, USA
http://www.whoi.edu/
http://www.whoi.edu/sbl/liteSite.do?litesiteid=7212
http://www.whoi.edu/hpb/Site.do?id=1532
http://www.whoi.edu/page.do?pid=10079
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