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Re: how to run hello world in on-chip ram?

by charlie yang :: Rate this Message:

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  Thanks Robert.
  I use the or1k/hello-uart as my example.   use or32-uclinux-objcopy to
get a hello.hex and initialize the on-chip ram. When use modelsim to do
rtl simulation, I find the on-chip ram input address(wb_ss_adr_i)  repeat
like 0x100,0x000,0x104,0x00,0x100,0x000,0x104,0x000. and the ouput
data (wb_ss_dat_o)  is  always zero.
 
   In the hello-uart,  there is no FLASH,no Memory controller and no
cache. I don't know if my reset.S is incorrect or hex files is incorrect.
Please give me some hints. Thanks!

Here is my reset.S in hello-uart directory:
        .global ___main
        .section .stack  /*, "aw", @nobits*/
.space  STACK_SIZE
_stack:

        .section .vectors, "ax"
        .org 0x100
       
_reset_vector:
        l.nop
        l.nop
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0

        l.movhi r3,hi(SDRAM_BASE_ADDR)
        l.ori   r3,r3,lo(SDRAM_BASE_ADDR)
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
        .section .text

_start:
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2  
 
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.nop

___main:
        l.jr r9
        l.nop

Then I use the following step to generate hex file:
or32-uclinux-gcc -g -c -o reset.o reset.S
or32-uclinux-ld -Tram.ld -o hello.or32 reset.o hello.o
or32-uclinux-objcopy -O binary hello.or32 hello.bin
or32-uclinux-objcopy -S -O ihex hello.or32 hello.hex


----- Original Message -----
From: Robert Cragie<rcc@j...>
To:
Date: Mon Nov 19 09:24:52 CET 2007
Subject: [openrisc] how to run hello world in on-chip ram?

> 1) The CPU always vectors to 0x100 on reset so you will either need
> some
> sort of bootstrap there or you will have to map RAM which you can
> download
> to there.
> 2) You can always get to intelhex from the ELF file using:
> or32-uclinux-objcopy -S -O ihex <ELFfile> <ihexfile>
> Robert Cragie, Design Engineer
>
_____________________________________________________________
__
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> http://www.jennic.com Tel: +44 (0) 114 281 2655
>
_____________________________________________________________
__

> > -----Original Message-----
> > From: openrisc-bounces at opencores.org
> > [mailto:openrisc-bounces at opencores.org]On Behalf Of charlie
> yang
> > Sent: 19 November 2007 04:17
> > To: openrisc at opencores.org
> > Subject: [openrisc] how to run hello world in on-chip ram?
> >
> >
> > hi all,
> > I have a altera FPGA board with Cyclone II EP2c35 and
> synthesize the
> > orp_soc following the hardware tutorials. I have only one
> dedicated
> > JTAG for FPGA and have no pins for or1k CPU. So I want to burn
> > the "hello world" program into on-chip ram by
> initializing this memory,
> > that is, let the JTAG download the all the CPU and program .
> > so there are two questions for help:
> > 1) how to set start pointer of the reset.S and let the
> "hello
> > world" run.
> > 2) I find the hello.hex in or1k is incompatible with Intel hex
> > format of
> > altera memory. how can I convert it to altera memory format?
> >
> > Is there anybody using altera FPGA? Please give me some
> directions .
> > Thanks a lot !
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/openrisc 
>
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

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