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Re: or1ksim 's question
by Matjaz Breskvar-5
::
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Hi Yeung,
The or1ksim cycles count is not very accurate, and even if you set the right
memory delays it is just a rough esstimation.
Having said that, the toolchain for OpenRISC is very unoptimized and the
OpenRISC itself is lacking in some areas. To improve all that the Beyond
Semiconductor was founded by the creators of OpenRISC. First we have
cosiderably optimized the OpenRISC RTL, and the result is Beyond BA12
processor, fully backwards compatible. Things that could not be improved due
to instruction set were addressed with Beyond BA22 which features the world
highest code density and has ~55% clock-for-clock performance increase
comparing to OpenRISC (with optimized toolchain).
Another interesting product is BA14 processor, an out-of-order dual issue
processor, which offers ~10x performance comparing to OpenRISC.
Currently we are in discussion how to offer all this developments to
comunity in a way not to disturb the founding such development requires.
Hopefully things get wrapped up soon.
For more info on OpenRISC compatible processors (in the sense that only
sofware recompile is needed) and peripherals you may visit our website at:
http://www.beyondsemi.com/
Yeung, please feel free to contact me, if you'd like to evaluate performance
of our processors with optimized toolchains against ARM. Te results will be
much more favorable.
best regards,
matjaz.
* yueng (penguin00@...) wrote:
>
> thanks
>
> i just want to compare or1k's perfomance with arm7 or arm9, so i use some
> algorithm ,for example
> jpeg decode run both on or1k and arm. to see which one use less cycles.
> and my result is or1ksim use 300M cycle and 200M instruction to finish a
> 320x240 jpegdecode compared
> with arm7 50M cycle and 40M instruction.
>
>
>
> Dimitri?s Orfanos wrote:
> >
> > Oh, and something else. I am not a maintainer of this project but I've
> > involved because of my university has put me an assignment(actually a
> > master thesis). So by reading the code of the or1ksim0.2.0 I have
> > concluded that there is no good measuring of cycles so I've done
> > something else. I've set on my own some CPI(clocks per instruction) and
> > with little scripting I can see which commands are executed (from the
> > executed.log) and how many times these commands are executed and I
> > calculate the total cycles of my own. For example I've set that the
> > "l.and" command uses 1 cycle if with my little script sees that there
> > are 3 "l.and" I measure 3*1 total cycles. The simulator uses a scheduler
> > which every n cycles tries to communicate with virtual devices that are
> > defined in the sim.cfg like keyboard, uart, etc . These cycles are also
> > added in the simulation cycles, so there is not so accurate. If you want
> > to use the simulator for cycle counting do something similar with me
> > make a little script and count the commands from the executed.log . If
> > you just want to use the simulator to run programs then you don't need
> > to count cycles.
> > DO
> >
> > yueng wrote:
> >> I change the sim.cfg , mem read and write both delay 1.
> >> i run jpeg decode in the or1ksim
> >> the result is
> >> 310,200,242 cycles, 171,816,396 instructions
> >> compare with arm7 it use only 56,000,000 cycle, and 40,000,000
> >> instructions
> >>
> >> i remember that i read or1ksim is about 90% cycle accurate somewhere,
> >> same jpeg decode C code ,why or1ksim use so many instructions? and so
> >> many
> >> cycles.
> >>
> >>
> >> thank you
> >>
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/openrisc
> >
> >
>
> --
> View this message in context: http://www.nabble.com/or1ksim-%27s-question-tp15540185p15582468.html
> Sent from the OpenCores - RISC mailing list archive at Nabble.com.
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
The or1ksim cycles count is not very accurate, and even if you set the right
memory delays it is just a rough esstimation.
Having said that, the toolchain for OpenRISC is very unoptimized and the
OpenRISC itself is lacking in some areas. To improve all that the Beyond
Semiconductor was founded by the creators of OpenRISC. First we have
cosiderably optimized the OpenRISC RTL, and the result is Beyond BA12
processor, fully backwards compatible. Things that could not be improved due
to instruction set were addressed with Beyond BA22 which features the world
highest code density and has ~55% clock-for-clock performance increase
comparing to OpenRISC (with optimized toolchain).
Another interesting product is BA14 processor, an out-of-order dual issue
processor, which offers ~10x performance comparing to OpenRISC.
Currently we are in discussion how to offer all this developments to
comunity in a way not to disturb the founding such development requires.
Hopefully things get wrapped up soon.
For more info on OpenRISC compatible processors (in the sense that only
sofware recompile is needed) and peripherals you may visit our website at:
http://www.beyondsemi.com/
Yeung, please feel free to contact me, if you'd like to evaluate performance
of our processors with optimized toolchains against ARM. Te results will be
much more favorable.
best regards,
matjaz.
* yueng (penguin00@...) wrote:
>
> thanks
>
> i just want to compare or1k's perfomance with arm7 or arm9, so i use some
> algorithm ,for example
> jpeg decode run both on or1k and arm. to see which one use less cycles.
> and my result is or1ksim use 300M cycle and 200M instruction to finish a
> 320x240 jpegdecode compared
> with arm7 50M cycle and 40M instruction.
>
>
>
> Dimitri?s Orfanos wrote:
> >
> > Oh, and something else. I am not a maintainer of this project but I've
> > involved because of my university has put me an assignment(actually a
> > master thesis). So by reading the code of the or1ksim0.2.0 I have
> > concluded that there is no good measuring of cycles so I've done
> > something else. I've set on my own some CPI(clocks per instruction) and
> > with little scripting I can see which commands are executed (from the
> > executed.log) and how many times these commands are executed and I
> > calculate the total cycles of my own. For example I've set that the
> > "l.and" command uses 1 cycle if with my little script sees that there
> > are 3 "l.and" I measure 3*1 total cycles. The simulator uses a scheduler
> > which every n cycles tries to communicate with virtual devices that are
> > defined in the sim.cfg like keyboard, uart, etc . These cycles are also
> > added in the simulation cycles, so there is not so accurate. If you want
> > to use the simulator for cycle counting do something similar with me
> > make a little script and count the commands from the executed.log . If
> > you just want to use the simulator to run programs then you don't need
> > to count cycles.
> > DO
> >
> > yueng wrote:
> >> I change the sim.cfg , mem read and write both delay 1.
> >> i run jpeg decode in the or1ksim
> >> the result is
> >> 310,200,242 cycles, 171,816,396 instructions
> >> compare with arm7 it use only 56,000,000 cycle, and 40,000,000
> >> instructions
> >>
> >> i remember that i read or1ksim is about 90% cycle accurate somewhere,
> >> same jpeg decode C code ,why or1ksim use so many instructions? and so
> >> many
> >> cycles.
> >>
> >>
> >> thank you
> >>
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/openrisc
> >
> >
>
> --
> View this message in context: http://www.nabble.com/or1ksim-%27s-question-tp15540185p15582468.html
> Sent from the OpenCores - RISC mailing list archive at Nabble.com.
>
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc
http://www.opencores.org/mailman/listinfo/openrisc
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