Regarding JOP

[Tan]

Martin Schoeberl wrote:

> I am uploading the code which I changed.I removed mem_sc_if block because I
> need only io interface.I also modified scio and added sc2wb into that.There
> is no error in the synthesis,however the simulation is not showing any
> results.Please help me out if there are any modifications required.

Where do you 'upload' your code?
Why did you remove mem_sc_if? You need a main memory for JOP
and this memory is attached by mem_sc_if.

Martin

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

jop-top.vhdmodified-scio.vhd

[Tan]

I have uploaded generated blocks and also the code.
please let me know if modifications are needed.
thanks
Cheers
tan

Tan wrote:

Martin Schoeberl wrote:

> I am uploading the code which I changed.I removed mem_sc_if block because I
> need only io interface.I also modified scio and added sc2wb into that.There
> is no error in the synthesis,however the simulation is not showing any
> results.Please help me out if there are any modifications required.

Where do you 'upload' your code?
Why did you remove mem_sc_if? You need a main memory for JOP
and this memory is attached by mem_sc_if.

Martin

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

jop-top.vhdmodified-scio.vhd

[Tan]

Here is another program with sc_mem_if.vhd block.Both the code which I sent you got synthesised but not showing results when the data is passe through input pin(wr_data).
can you please tell me where the data should be forced to.Is it from "wr_data" pin???
cheers
tan

I have uploaded generated blocks and also the code.
please let me know if modifications are needed.
thanks
Cheers
tan

Tan wrote:

Martin Schoeberl wrote:

> I am uploading the code which I changed.I removed mem_sc_if block because I
> need only io interface.I also modified scio and added sc2wb into that.There
> is no error in the synthesis,however the simulation is not showing any
> results.Please help me out if there are any modifications required.

Where do you 'upload' your code?
Why did you remove mem_sc_if? You need a main memory for JOP
and this memory is attached by mem_sc_if.

Martin

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

jop-top.vhdmodified-scio.vhd

[Martin Schoeberl]

Hi Tan,

attaching files is useless in this group as there are
no attachments allowed - which is good BTW!

>
> Here is another program with sc_mem_if.vhd block.Both the code which I sent
> you got synthesised but not showing results when the data is passe through
> input pin(wr_data).
> can you please tell me where the data should be forced to.Is it from
> "wr_data" pin???

wr_data is not a 'pin' it's a 32-bit data connection.
For a description of the SimpCon interface see:
http://www.opencores.org/projects.cgi/web/simpcon/overview

Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

Hi martin,
Can you give me your mail id so that I can send my code.
BTW I didnot understand what you said.
Cheers
Tan

Martin Schoeberl wrote:

Hi Tan,

attaching files is useless in this group as there are
no attachments allowed - which is good BTW!

>
> Here is another program with sc_mem_if.vhd block.Both the code which I sent
> you got synthesised but not showing results when the data is passe through
> input pin(wr_data).
> can you please tell me where the data should be forced to.Is it from
> "wr_data" pin???

wr_data is not a 'pin' it's a 32-bit data connection.
For a description of the SimpCon interface see:
http://www.opencores.org/projects.cgi/web/simpcon/overview

Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Martin Schoeberl]

Hi Tan,

there is some communication issue between you and me: I ask
you questions to get down to the real problem, but you
are not giving me an answer. Perhaps there is a more
fundamental issue than just getting JOP work with
an Wishbone attached IO device.

> Can you give me your mail id so that I can send my code.

I'm not sure if I want to get spammed with images and
code fragments. BTW: my time is limited and I canot be
your debugger ;-)

> BTW I didnot understand what you said.

Have you looked into the document I sent you the
link? If yes, than you're quite fast with the
reading...

Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

Hi
Sorry If I am bothering you too much.Actually I am stuck in my project so posted the question.
Yeah I will go through the document.Thanks for your immediate response.
cheers
Tan

Martin Schoeberl wrote:

Hi Tan,

there is some communication issue between you and me: I ask
you questions to get down to the real problem, but you
are not giving me an answer. Perhaps there is a more
fundamental issue than just getting JOP work with
an Wishbone attached IO device.

> Can you give me your mail id so that I can send my code.

I'm not sure if I want to get spammed with images and
code fragments. BTW: my time is limited and I canot be
your debugger ;-)

> BTW I didnot understand what you said.

Have you looked into the document I sent you the
link? If yes, than you're quite fast with the
reading...

Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

Martin

I am extremely sorry for being such a pain. The thing is I am stuck in my project work with my deadline
just a couple of days away.With the issue refusing to budge and with no alternative in sight, my communication too had turned incoherent. I hope you understand.

>>
I'm not sure if I want to get spammed with images and code fragments. BTW: my time is limited and I canot be your debugger ;-)

That was not my intention Martin. I had to resort to asking you to have a look at my code as I had no other option and I was unable to clearly explain my problem. I thought showing you my code would give you an idea of the problem.

>>Have you looked into the document I sent you the link? If yes, than you're quite fast with the
reading...

:-) Trust me Martin, I have indeed read the document. Infact I read it a week back. As I am working on Simpcon, I downloaded the pdf from opencores.org. Infact I am quite sure that the answer to my problem is explained under the Examples section of the document (Section 4). However it could be because I am a newbie that I havent clearly understood that section. My colleagues who help me with this have read it as well but they havent grasped it either.Some more projects and I am sure I will be in a better position to understand and then hopefully I shall stop being a pest. Till then I have no other option but to seek your help. Please do understand.

As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you remember you had once advised me to change the scio_dspio.vhd. I had changed it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd had a counter,a UART, a usb and  sc2wb. Since I wanted to use only sc2wb, I disabled  the UART and the USB blocks.

I am pasting the modified code below:
-- SimpCon Wishbone bridge
        cmp_wb: entity work.sc2wb generic map (
                        addr_bits => SLAVE_ADDR_BITS
                )
                port map(
                        clk => clk,
                        reset => reset,
                        address => address(SLAVE_ADDR_BITS-1 downto 0),
                        wr_data => wr_data,
                        rd => sc_rd(1),
                        wr => sc_wr(1),
                        rd_data => sc_dout(1),
                        rdy_cnt => sc_rdy_cnt(1),
                        wb_out => wb_out,
                        wb_in => wb_in );

I have also disabled the ser_txd pin in the top module(as I am not using UArt). In its place I have defined the ports of sc2wb and I2S in the top module.(as I am interfacing JOP to I2S my input has to go through JOp and the output has to come from I2S)

Code pasted below:

port (
        clk : in std_logic;
        rd_data :in std_logic_vector(31 downto 0);

      --wr_data:out std_logic_vector(31 downto 0);    
               
        sc_rd_data :  inout std_logic_vector(31 downto 0);
        sc_wr_data :  inout  std_logic_vector(31 downto 0);
         

--- watchdog
--
        wd : out std_logic;


          tx_i2s_sck            :  out std_logic;
         tx_i2s_sd : out std_logic;
         tx_i2s_ws : out std_logic;
         tx_i2s_int :out  std_logic;


--
-- two ram banks
--
        ram_addr : out std_logic_vector(17 downto 0);
        ram_nwe : out std_logic;
        ram_noe : out std_logic;
        rama_d : inout std_logic_vector(15 downto 0);
        rama_ncs : out std_logic;
        rama_nlb : out std_logic;
        rama_nub : out std_logic;
        ramb_d : inout std_logic_vector(15 downto 0);
        ramb_ncs : out std_logic;
        ramb_nlb : out std_logic;
        ramb_nub : out std_logic
);
end jop;

This is the top module entity.The synthesis works fine but during simulation,when I force the value to wr_data,there is no respone from tx_i2s_sd. Do you see anything obviously wrong in what I have done?
Also if there are any questions for which you need answers to help me with this, do let me know.  


Thanks...Tan

p.s. The 'fatal error' that I had mentioned the other day has now been corrected. It probably was because many slaves were connected to the master. aND the Xilinx version I am using does not like it.After disabling the UART and USB components, the problem disappeared.

Martin Schoeberl wrote:

Hi Tan,

there is some communication issue between you and me: I ask
you questions to get down to the real problem, but you
are not giving me an answer. Perhaps there is a more
fundamental issue than just getting JOP work with
an Wishbone attached IO device.

> Can you give me your mail id so that I can send my code.

I'm not sure if I want to get spammed with images and
code fragments. BTW: my time is limited and I canot be
your debugger ;-)

> BTW I didnot understand what you said.

Have you looked into the document I sent you the
link? If yes, than you're quite fast with the
reading...

Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

This is in continuation to the previous mail,I am pasting the top-scio's entity


entity scio is
generic (addr_bits : integer);

port (
        clk : in std_logic;
        reset : in std_logic;

-- SimpCon interface

        address : in std_logic_vector(addr_bits-1 downto 0);
        wr_data : in std_logic_vector(31 downto 0);
        rd, wr : in std_logic;
        rd_data : out std_logic_vector(31 downto 0);
        rdy_cnt : out unsigned(1 downto 0);

-- interrupt

        irq : out std_logic;
        irq_ena : out std_logic;

-- exception

        exc_req : in exception_type;
        exc_int : out std_logic;





-- serial interface

-- txd : out std_logic;
-- rxd : in std_logic;
-- ncts : in std_logic;

-- watch dog

        wd : out std_logic;

-- core i/o pins
        l : inout std_logic_vector(20 downto 1);
        r : inout std_logic_vector(20 downto 1);
        t : inout std_logic_vector(6 downto 1);
        b : inout std_logic_vector(10 downto 1);


         tx_i2s_sck : out std_logic;
         tx_i2s_sd :  out std_logic;
         tx_i2s_ws : out std_logic;
            tx_i2s_int :  out std_logic




);
end scio;

Martin Schoeberl wrote:

Hi Tan,

there is some communication issue between you and me: I ask
you questions to get down to the real problem, but you
are not giving me an answer. Perhaps there is a more
fundamental issue than just getting JOP work with
an Wishbone attached IO device.

> Can you give me your mail id so that I can send my code.

I'm not sure if I want to get spammed with images and
code fragments. BTW: my time is limited and I canot be
your debugger ;-)

> BTW I didnot understand what you said.

Have you looked into the document I sent you the
link? If yes, than you're quite fast with the
reading...

Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Martin Schoeberl]

Hi Tan,

> That was not my intention Martin. I had to resort to asking you to have a
> look at my code as I had no other option and I was unable to clearly explain
> my problem. I thought showing you my code would give you an idea of the
> problem.

You could upload your code to a website and provde a link to it
in the posting. That's a less intrusive way ;-)

> As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you
> remember you had once advised me to change the scio_dspio.vhd. I had changed
> it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd
> had a counter,a UART, a usb and  sc2wb. Since I wanted to use only sc2wb, I
> disabled  the UART and the USB blocks.

Do you want to run your design in hardware (FPGA) or just in
a ModelSim simulation?

If you want to run it in an FPGA you need the UART. How would
you download the Java program without a communication path
between your PC and JOP?

Even in the ModelSim simulation the UART makes sense. You
can debug your Java program with print outs. System.out.println()
goes to the UART.

So, there is no reason to remove the UART from the design.

> I am pasting the modified code below:
> -- SimpCon Wishbone bridge
> cmp_wb: entity work.sc2wb generic map (
> addr_bits => SLAVE_ADDR_BITS
> )
> port map(
> clk => clk,
> reset => reset,
> address => address(SLAVE_ADDR_BITS-1 downto 0),
> wr_data => wr_data,
> rd => sc_rd(1),
> wr => sc_wr(1),
> rd_data => sc_dout(1),
> rdy_cnt => sc_rdy_cnt(1),
> wb_out => wb_out,
> wb_in => wb_in );

looks ok, that's the same as in scio_dspio.vhd.

>   tx_i2s_sck             :  out std_logic;
> tx_i2s_sd : out std_logic;
> tx_i2s_ws : out std_logic;
> tx_i2s_int :out  std_logic;

looks, like you are only using transmit. No receive
port, right?

> This is the top module entity.The synthesis works fine but during
> simulation,when I force the value to wr_data,there is no respone from
> tx_i2s_sd. Do you see anything obviously wrong in what I have done?

Yes, this is the main issue.

Think about a processor (JOP is a processor). When you force just
a value on the data bus, where the processor usually reads instructions
and reads and writes values. What you you think what the processor
will do?

JOP (and each processor) will do nothing usefull without a program!
So you have to write your application (for JOP in Java) and download
it to the RAM.

Start with a simple 'Hello World' and run this in the simulation
or on the real hardware. Use the unmodified code first!!!

Than add your I2S interface and see if 'Hello World' still
runns.

That's my way to perform changes to a unknown project. First
get it unmodified running THAN apply the changes. I do this
even when I'm working with JOP - first a clean, working
strating point.

Cheers,
Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

Thanks Martin.

>>You could upload your code to a website and provde a link to it
>>in the posting. That's a less intrusive way ;-)

Alright Martin. I shall do this henceforth.

>>Do you want to run your design in hardware (FPGA) or just in
>>a ModelSim simulation?

Both. So I would need to have UART enabled.

>>If you want to run it in an FPGA you need the UART. How would
>>you download the Java program without a communication path
>>between your PC and JOP?

>>Even in the ModelSim simulation the UART makes sense. You
>>can debug your Java program with print outs. System.out.println()
>>goes to the UART.

>>So, there is no reason to remove the UART from the design.

Got it ! I shall rectify this.

>>looks, like you are only using transmit. No receive
>>port, right?

Yes thats how it is.

>>JOP (and each processor) will do nothing usefull without a program!
>>So you have to write your application (for JOP in Java) and download
>>it to the RAM.

Cheers Martin. I shall do this tomorrow and revert to you with my results (and new queries if any :-) )

Thanks again...Tan.

p.s I have acknowledged all your help in the introduction of my Project thesis work.  I shall be uploading it to opencores.org after my launch and presentation scheduled on the 1st of Sept.

Martin Schoeberl wrote:

Hi Tan,

> That was not my intention Martin. I had to resort to asking you to have a
> look at my code as I had no other option and I was unable to clearly explain
> my problem. I thought showing you my code would give you an idea of the
> problem.

You could upload your code to a website and provde a link to it
in the posting. That's a less intrusive way ;-)

> As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you
> remember you had once advised me to change the scio_dspio.vhd. I had changed
> it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd
> had a counter,a UART, a usb and  sc2wb. Since I wanted to use only sc2wb, I
> disabled  the UART and the USB blocks.

Do you want to run your design in hardware (FPGA) or just in
a ModelSim simulation?

If you want to run it in an FPGA you need the UART. How would
you download the Java program without a communication path
between your PC and JOP?

Even in the ModelSim simulation the UART makes sense. You
can debug your Java program with print outs. System.out.println()
goes to the UART.

So, there is no reason to remove the UART from the design.

> I am pasting the modified code below:
> -- SimpCon Wishbone bridge
> cmp_wb: entity work.sc2wb generic map (
> addr_bits => SLAVE_ADDR_BITS
> )
> port map(
> clk => clk,
> reset => reset,
> address => address(SLAVE_ADDR_BITS-1 downto 0),
> wr_data => wr_data,
> rd => sc_rd(1),
> wr => sc_wr(1),
> rd_data => sc_dout(1),
> rdy_cnt => sc_rdy_cnt(1),
> wb_out => wb_out,
> wb_in => wb_in );

looks ok, that's the same as in scio_dspio.vhd.

>   tx_i2s_sck             :  out std_logic;
> tx_i2s_sd : out std_logic;
> tx_i2s_ws : out std_logic;
> tx_i2s_int :out  std_logic;

looks, like you are only using transmit. No receive
port, right?

> This is the top module entity.The synthesis works fine but during
> simulation,when I force the value to wr_data,there is no respone from
> tx_i2s_sd. Do you see anything obviously wrong in what I have done?

Yes, this is the main issue.

Think about a processor (JOP is a processor). When you force just
a value on the data bus, where the processor usually reads instructions
and reads and writes values. What you you think what the processor
will do?

JOP (and each processor) will do nothing usefull without a program!
So you have to write your application (for JOP in Java) and download
it to the RAM.

Start with a simple 'Hello World' and run this in the simulation
or on the real hardware. Use the unmodified code first!!!

Than add your I2S interface and see if 'Hello World' still
runns.

That's my way to perform changes to a unknown project. First
get it unmodified running THAN apply the changes. I do this
even when I'm working with JOP - first a clean, working
strating point.

Cheers,
Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

Hi Martin,
I am here with new questions :).

As per our disussion yesterday,I used jopsim,after that I gave "doit test test Helloworld",when i tried to simulate "sim" command and found the result positive.
Now when i tried the modified scio block which inludes sc2wb in it,it is giving the error at the end in scio block.

Below I am pasting the part of simulation result when executed on DOS.
Can you please tell me how to include the work library of sc2wb and i2S  for simulation..
 

.
C:\newjop\jop\modelsim>sim

C:\newjop\jop\modelsim>set jopdir=../vhdl

C:\newjop\jop\modelsim>rem set options=-93 -quiet -check_synthesis -lint -pedant
icerrors

C:\newjop\jop\modelsim>set options=-93 -quiet

C:\newjop\jop\modelsim>rmdir /S/Q work
The system cannot find the file specified.

C:\newjop\jop\modelsim>vlib work

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_jop_config_100.vhd


C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jop_types.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_ram.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_pll.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_jbc.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_rom.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_memory.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/fifo.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/scio/sc_uart.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/sim_sc_uart.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/wishbone/wb_pack.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/wishbone/wb_test_slave.vhd

C:\newjop\jop\modelsim>rem vcom -93 -quiet ../vhdl/wishbone/wb_top.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/jtbl.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/offtbl.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/cache.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/sc_sram32_flash.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/memory/mem_sc.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/mul.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/extension.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/bcfetch.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/fetch.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/decode.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/shift.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/stack.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/core/core.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/sc_cnt.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd
** Error: (vcom-11) Could not find work.sc2wb.
** Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded name:
 'work.sc2wb'.
** Error: ../vhdl/scio/scio_min.vhd(266): Unknown record element "sc2wb".
** Error: ../vhdl/scio/scio_min.vhd(287): Statement cannot be labeled.
** Error: ../vhdl/scio/scio_min.vhd(364): VHDL Compiler exiting

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/top/jopcyc.vhd

C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/simulation/tb_jop.vhd

C:\newjop\jop\modelsim>pause Start simulation?
Press any key to continue . . .

C:\newjop\jop\modelsim>vsim -do sim.do tb_jop
Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl

C:\newjop\jop\modelsim>cd ..

C:\newjop\jop>

Martin Schoeberl wrote:

Hi Tan,

> That was not my intention Martin. I had to resort to asking you to have a
> look at my code as I had no other option and I was unable to clearly explain
> my problem. I thought showing you my code would give you an idea of the
> problem.

You could upload your code to a website and provde a link to it
in the posting. That's a less intrusive way ;-)

> As per your advice yesterday, I enabled the mem_sc_if.vhd back. If you
> remember you had once advised me to change the scio_dspio.vhd. I had changed
> it by replacing the ac97 component with I2S.Additionally the scio_dspio.vhd
> had a counter,a UART, a usb and  sc2wb. Since I wanted to use only sc2wb, I
> disabled  the UART and the USB blocks.

Do you want to run your design in hardware (FPGA) or just in
a ModelSim simulation?

If you want to run it in an FPGA you need the UART. How would
you download the Java program without a communication path
between your PC and JOP?

Even in the ModelSim simulation the UART makes sense. You
can debug your Java program with print outs. System.out.println()
goes to the UART.

So, there is no reason to remove the UART from the design.

> I am pasting the modified code below:
> -- SimpCon Wishbone bridge
> cmp_wb: entity work.sc2wb generic map (
> addr_bits => SLAVE_ADDR_BITS
> )
> port map(
> clk => clk,
> reset => reset,
> address => address(SLAVE_ADDR_BITS-1 downto 0),
> wr_data => wr_data,
> rd => sc_rd(1),
> wr => sc_wr(1),
> rd_data => sc_dout(1),
> rdy_cnt => sc_rdy_cnt(1),
> wb_out => wb_out,
> wb_in => wb_in );

looks ok, that's the same as in scio_dspio.vhd.

>   tx_i2s_sck             :  out std_logic;
> tx_i2s_sd : out std_logic;
> tx_i2s_ws : out std_logic;
> tx_i2s_int :out  std_logic;

looks, like you are only using transmit. No receive
port, right?

> This is the top module entity.The synthesis works fine but during
> simulation,when I force the value to wr_data,there is no respone from
> tx_i2s_sd. Do you see anything obviously wrong in what I have done?

Yes, this is the main issue.

Think about a processor (JOP is a processor). When you force just
a value on the data bus, where the processor usually reads instructions
and reads and writes values. What you you think what the processor
will do?

JOP (and each processor) will do nothing usefull without a program!
So you have to write your application (for JOP in Java) and download
it to the RAM.

Start with a simple 'Hello World' and run this in the simulation
or on the real hardware. Use the unmodified code first!!!

Than add your I2S interface and see if 'Hello World' still
runns.

That's my way to perform changes to a unknown project. First
get it unmodified running THAN apply the changes. I do this
even when I'm working with JOP - first a clean, working
strating point.

Cheers,
Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Martin Schoeberl]

> As per our disussion yesterday,I used jopsim,after that I gave "doit test
> test Helloworld",when i tried to simulate "sim" command and found the result
> positive.

ok, fine.

> Now when i tried the modified scio block which inludes sc2wb in it,it is
> giving the error at the end in scio block.
>
> Below I am pasting the part of simulation result when executed on DOS.
> Can you please tell me how to include the work library of sc2wb and i2S  for
> simulation..

> C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd
> ** Error: (vcom-11) Could not find work.sc2wb.
> ** Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded
> name:
> 'work.sc2wb'.

You have to add your design file to the ModelSim project.
That means: add it to the sim.bat in the modelsim directory.

Martin

_______________________________________________
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[Tan]

Hi Martin,
>>You have to add your design file to the ModelSim project.
>>>That means: add it to the sim.bat in the modelsim directory.

How to include the design file into sim.bat???Can you please explain in detail..
I tried it but couldnot get any idea how to do that..
cheers
tan

Martin Schoeberl wrote:

> As per our disussion yesterday,I used jopsim,after that I gave "doit test
> test Helloworld",when i tried to simulate "sim" command and found the result
> positive.

ok, fine.

> Now when i tried the modified scio block which inludes sc2wb in it,it is
> giving the error at the end in scio block.
>
> Below I am pasting the part of simulation result when executed on DOS.
> Can you please tell me how to include the work library of sc2wb and i2S  for
> simulation..

> C:\newjop\jop\modelsim>vcom -93 -quiet ../vhdl/scio/scio_min.vhd
> ** Error: (vcom-11) Could not find work.sc2wb.
> ** Error: ../vhdl/scio/scio_min.vhd(266): (vcom-1195) Cannot find expanded
> name:
> 'work.sc2wb'.

You have to add your design file to the ModelSim project.
That means: add it to the sim.bat in the modelsim directory.

Martin

_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Martin Schoeberl]

>>>You have to add your design file to the ModelSim project.
>>>>That means: add it to the sim.bat in the modelsim directory.
>
> How to include the design file into sim.bat???Can you please explain in
> detail..

What about using a text editor and open sim.bat???


> I tried it but couldnot get any idea how to do that..

Add your VHDL files in the same way as the other files
are listed.
_______________________________________________
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[Tan]

Hi martin,
I got it...
I just right clicked the sim.bat and went to edit and modified it accordingly...
thanks so much for your help..
Tan

Martin Schoeberl wrote:

>>>You have to add your design file to the ModelSim project.
>>>>That means: add it to the sim.bat in the modelsim directory.
>
> How to include the design file into sim.bat???Can you please explain in
> detail..

What about using a text editor and open sim.bat???


> I tried it but couldnot get any idea how to do that..

Add your VHDL files in the same way as the other files
are listed.
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

Hi Martin,
I made further progress today,However I am stuck up at a point in testbench. JOP zip there is a testbench for cyclone board(tb_jop.vhd).I modified the testbench according to my project i.e.removed "flash ram".and also made some modifications in the component jop accordinglyincluded transmission pins of I2s) .I tried to use the same "memory" which you instantiated in the tb_jop.when iincluded the same memory in my testbench,modelsim is not responding and when i disabled those signals modelsim is responding but the data is not passed into wr_data pin(because i disabled memory).Can you please tell me  which memory to include.In my project I am using "mem_sc.vhd" and "sc_mem_if.vhd".Among these two blocks which memory should I include in my testbench in order to get output from ser_txd pin,and wr_data pin,so that the data can pass to I2s via wishbone..

Tan

Martin Schoeberl wrote:

>>>You have to add your design file to the ModelSim project.
>>>>That means: add it to the sim.bat in the modelsim directory.
>
> How to include the design file into sim.bat???Can you please explain in
> detail..

What about using a text editor and open sim.bat???


> I tried it but couldnot get any idea how to do that..

Add your VHDL files in the same way as the other files
are listed.
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Martin Schoeberl]

> please tell me  which memory to include.In my project I am using
> "mem_sc.vhd" and "sc_mem_if.vhd".Among these two blocks which memory should
> I include in my testbench in order to get output from ser_txd pin,and
> wr_data pin,so that the data can pass to I2s via wishbone..

Have you written your Java application that writes some
data to your I2S interface?

Martin
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Tan]

Hi Martin,
Thank you so much for your help.
I would not have completed my project if youwould not have helped me and cleared my doubts.
You rescued me like god.
thanks so much.
i have added your name in my acknowledgement list of my project report.

Martin Schoeberl wrote:

>>>You have to add your design file to the ModelSim project.
>>>>That means: add it to the sim.bat in the modelsim directory.
>
> How to include the design file into sim.bat???Can you please explain in
> detail..

What about using a text editor and open sim.bat???


> I tried it but couldnot get any idea how to do that..

Add your VHDL files in the same way as the other files
are listed.
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores

[Martin Schoeberl]

> Hi Martin,
> Thank you so much for your help.
> I would not have completed my project if youwould not have helped me and
> cleared my doubts.
> You rescued me like god.
> thanks so much.
> i have added your name in my acknowledgement list of my project report.

Ok, thanks. Do you have a link to your project report, so
we can read about your results?

Martin
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