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Regarding the hardware of OR1200 related to cache

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	Regarding the hardware of OR1200 related to cache by Pradip Harindran :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message Hello, We are a group of two, involved in a project to redesign the cache module present in OR1200. To do this we need to understand the various signals going in and out of the cache and qmem modules. We havent understood some of the signals like cycstb, ci, sel, tag, rty. It would be helpful if someone could provide us with this information or point us to a documentation which gives us a description of all the signals used in OR1200. Thanking you, Pradip Cherin _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc
	RE: Regarding the hardware of OR1200 related to cache by Richard Herveille :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message Some parts of this message have been removed. Learn more about Nabble's security policy. These are wishone signals. Download the wishbone spec from opencores. Richard From: openrisc-bounces@... [mailto:openrisc-bounces@...] On Behalf Of Pradip Harindran Sent: 19 February 2009 18:45 To: openrisc@... Subject: [openrisc] Regarding the hardware of OR1200 related to cache Hello, We are a group of two, involved in a project to redesign the cache module present in OR1200. To do this we need to understand the various signals going in and out of the cache and qmem modules. We havent understood some of the signals like cycstb, ci, sel, tag, rty. It would be helpful if someone could provide us with this information or point us to a documentation which gives us a description of all the signals used in OR1200. Thanking you, Pradip Cherin _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc
	RE: Regarding the hardware of OR1200 related to cache by Jeremy Bennett-4 :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message On Fri, 2009-02-20 at 08:47 +0100, Richard Herveille wrote: > These are wishone signals. > > Download the wishbone spec from opencores. Hi Richard, In the OpenRISC code, the CAB signal is used, but I believe this was dropped from Wishbone even before version 1 of the standard. Can you tell us what this signal was for. Just curiosity for understanding the code. Thanks, Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett@... Web: www.embecosm.com _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc
	Re: Regarding the hardware of OR1200 related to cache by Jose Ignacio Villar-2 :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message Hi! I think that this signal was dropped from a Wishbone Spec prior to B.3. I remember that It meant Cycle Address Burst or something like this. Regards, Jose. -- José Ignacio Villar <jose@...> Departamento de Tecnología Electrónica Escuela Técnica Superior de Ingeniería Informática Universidad de Sevilla Avda. Reina Mercedes, s/n 41012 - Sevilla (Spain) Tlf: 954 55 61 60 Fax: 954 55 27 64 On Fri, Feb 20, 2009 at 4:12 PM, Jeremy Bennett <jeremy.bennett@...> wrote: On Fri, 2009-02-20 at 08:47 +0100, Richard Herveille wrote: > These are wishone signals. > > Download the wishbone spec from opencores. Hi Richard, In the OpenRISC code, the CAB signal is used, but I believe this was dropped from Wishbone even before version 1 of the standard. Can you tell us what this signal was for. Just curiosity for understanding the code. Thanks, Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett@... Web: www.embecosm.com _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc
	RE: Regarding the hardware of OR1200 related to cache by Richard Herveille :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message CAB is way obsolete :) It momentarily saw light inbetween RevB2 and RevB3. It mean Continuous Address Burst. It is superseded by CTI and BTE. Somebody should really change this in the OpenRISC. CAB can only operate on linear address ranges, whereas CTI/BTE allows for interleaved (as used by the cache controller) address schemes. Richard -----Original Message----- From: openrisc-bounces@... [mailto:openrisc-bounces@...] On Behalf Of Jeremy Bennett Sent: 20 February 2009 16:12 To: List about OpenRISC project Subject: RE: [openrisc] Regarding the hardware of OR1200 related to cache On Fri, 2009-02-20 at 08:47 +0100, Richard Herveille wrote: > These are wishone signals. > > Download the wishbone spec from opencores. Hi Richard, In the OpenRISC code, the CAB signal is used, but I believe this was dropped from Wishbone even before version 1 of the standard. Can you tell us what this signal was for. Just curiosity for understanding the code. Thanks, Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett@... Web: www.embecosm.com _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc
	Re: Regarding the hardware of OR1200 related to cache by Pradip Harindran :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message Thank you for the info. We have gone through the wishbone documentation and we could find a good amount of info on the signals. But i couldnt find anything on the cab signal anywhere. It would be helpful if you could provide some more info on it as we have to work on the cache module. Thanking you, Pradip On Fri, Feb 20, 2009 at 11:13 PM, Richard Herveille <richard@...> wrote: CAB is way obsolete :) It momentarily saw light inbetween RevB2 and RevB3. It mean Continuous Address Burst. It is superseded by CTI and BTE. Somebody should really change this in the OpenRISC. CAB can only operate on linear address ranges, whereas CTI/BTE allows for interleaved (as used by the cache controller) address schemes. Richard -----Original Message----- From: openrisc-bounces@... [mailto:openrisc-bounces@...] On Behalf Of Jeremy Bennett Sent: 20 February 2009 16:12 To: List about OpenRISC project Subject: RE: [openrisc] Regarding the hardware of OR1200 related to cache On Fri, 2009-02-20 at 08:47 +0100, Richard Herveille wrote: > These are wishone signals. > > Download the wishbone spec from opencores. Hi Richard, In the OpenRISC code, the CAB signal is used, but I believe this was dropped from Wishbone even before version 1 of the standard. Can you tell us what this signal was for. Just curiosity for understanding the code. Thanks, Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett@... Web: www.embecosm.com _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc
	RE: Regarding the hardware of OR1200 related to cache by Richard Herveille :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message Some parts of this message have been removed. Learn more about Nabble's security policy. If other people agree then I suggest you remove the CAB signal and replace it with the appropriate CTI and BTE signals. CAB is obsolete and really should be removed from any cores (including the or1200) that still use it. Richard From: openrisc-bounces@... [mailto:openrisc-bounces@...] On Behalf Of Pradip Harindran Sent: 03 March 2009 12:55 To: List about OpenRISC project Subject: Re: [openrisc] Regarding the hardware of OR1200 related to cache Thank you for the info. We have gone through the wishbone documentation and we could find a good amount of info on the signals. But i couldnt find anything on the cab signal anywhere. It would be helpful if you could provide some more info on it as we have to work on the cache module. Thanking you, Pradip On Fri, Feb 20, 2009 at 11:13 PM, Richard Herveille <richard@...> wrote: CAB is way obsolete :) It momentarily saw light inbetween RevB2 and RevB3. It mean Continuous Address Burst. It is superseded by CTI and BTE. Somebody should really change this in the OpenRISC. CAB can only operate on linear address ranges, whereas CTI/BTE allows for interleaved (as used by the cache controller) address schemes. Richard -----Original Message----- From: openrisc-bounces@... [mailto:openrisc-bounces@...] On Behalf Of Jeremy Bennett Sent: 20 February 2009 16:12 To: List about OpenRISC project Subject: RE: [openrisc] Regarding the hardware of OR1200 related to cache On Fri, 2009-02-20 at 08:47 +0100, Richard Herveille wrote: > These are wishone signals. > > Download the wishbone spec from opencores. Hi Richard, In the OpenRISC code, the CAB signal is used, but I believe this was dropped from Wishbone even before version 1 of the standard. Can you tell us what this signal was for. Just curiosity for understanding the code. Thanks, Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett@... Web: www.embecosm.com _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc
	Re: Regarding the hardware of OR1200 related to cache by Jose Ignacio Villar :: Rate this Message: Reply to Author \| View Threaded \| Show Only this Message Hello, I think it's a good idea to remove cab signals. Many of as have had to investigate its meaning and origin now that it is not being mentioned in Wishbone Specs anymore. It will help to avoid confusion in the future. Jose. -- José Ignacio Villar <jose@...> Departamento de Tecnología Electrónica Escuela Técnica Superior de Ingeniería Informática Universidad de Sevilla Avda. Reina Mercedes, s/n 41012 - Sevilla (Spain) Tlf: 954 55 61 60 Fax: 954 55 27 64 On Wed, Mar 4, 2009 at 8:12 AM, Richard Herveille <richard@...> wrote: If other people agree then I suggest you remove the CAB signal and replace it with the appropriate CTI and BTE signals. CAB is obsolete and really should be removed from any cores (including the or1200) that still use it. Richard From: openrisc-bounces@... [mailto:openrisc-bounces@...] On Behalf Of Pradip Harindran Sent: 03 March 2009 12:55 To: List about OpenRISC project Subject: Re: [openrisc] Regarding the hardware of OR1200 related to cache Thank you for the info. We have gone through the wishbone documentation and we could find a good amount of info on the signals. But i couldnt find anything on the cab signal anywhere. It would be helpful if you could provide some more info on it as we have to work on the cache module. Thanking you, Pradip On Fri, Feb 20, 2009 at 11:13 PM, Richard Herveille <richard@...> wrote: CAB is way obsolete :) It momentarily saw light inbetween RevB2 and RevB3. It mean Continuous Address Burst. It is superseded by CTI and BTE. Somebody should really change this in the OpenRISC. CAB can only operate on linear address ranges, whereas CTI/BTE allows for interleaved (as used by the cache controller) address schemes. Richard -----Original Message----- From: openrisc-bounces@... [mailto:openrisc-bounces@...] On Behalf Of Jeremy Bennett Sent: 20 February 2009 16:12 To: List about OpenRISC project Subject: RE: [openrisc] Regarding the hardware of OR1200 related to cache On Fri, 2009-02-20 at 08:47 +0100, Richard Herveille wrote: > These are wishone signals. > > Download the wishbone spec from opencores. Hi Richard, In the OpenRISC code, the CAB signal is used, but I believe this was dropped from Wishbone even before version 1 of the standard. Can you tell us what this signal was for. Just curiosity for understanding the code. Thanks, Jeremy -- Tel: +44 (1202) 416955 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: jeremy.bennett@... Web: www.embecosm.com _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc