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Request to commit: HS16 + OSR changes for ARM

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Request to commit: HS16 + OSR changes for ARM

by Edward Nevill-3 :: Rate this Message:

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Hi Folks,

The following changes make hs16 work for ARM and add OSR support for Shark. The files
affected are

- asm_helper.cpp
- bytecodes_arm.def
- cppInterpreter_arm.S
- sharkCacheDecache.cpp

The last change (sharkCacheDecache.cpp) is to fix an 'Unimplemented()' error when a
method with multiple monitors is OSRed. I have discussed this change with Gary.

Gary? Are you happy with the change to sharkCacheDecache.cpp?

It has been suggested by Gary that if the changes are purely to ARM code then I should
just commit. Andrew has said that he would prefer such changes were posted for
discussion. Would it be a reasonable comproise to say that if the changes are posted,
and there are no objections within 24 hours  then I can just go ahead and commit the changes
(this would only apply to files which are ARM only).

In the above case the 1st 3 files would not need approval, since they are ARM only. The
last would need Gary's approval.

Regards,
Ed.

--- CUT HERE -------------------------------------------------------------------------------
diff -ruNE old/icedtea6/ports/hotspot/src/cpu/zero/vm/asm_helper.cpp new/icedtea6/ports/hotspot/src/cpu/zero/vm/asm_helper.cpp
--- old/icedtea6/ports/hotspot/src/cpu/zero/vm/asm_helper.cpp 2009-11-04 11:33:19.000000000 +0000
+++ new/icedtea6/ports/hotspot/src/cpu/zero/vm/asm_helper.cpp 2009-11-04 11:41:06.000000000 +0000
@@ -110,6 +110,7 @@
  print_def("METHOD_NATIVEHANDLER", sizeof(methodOopDesc));
  print_def("METHOD_SIGNATUREHANDLER", sizeof(methodOopDesc)+4);
  nl();
+        print_def("CONSTMETHOD_CODESIZE", offset_of(constMethodOopDesc, _code_size));
  print_def("CONSTMETHOD_CODEOFFSET", sizeof(constMethodOopDesc));
  nl();
  print_def("JNIHANDLEBLOCK_TOP", offset_of(JNIHandleBlock, _top));
@@ -124,6 +125,14 @@
  nl();
  print_def("CONSTANTPOOL_TAGS", offset_of(constantPoolOopDesc, _tags));
  print_def("CONSTANTPOOL_CACHE", offset_of(constantPoolOopDesc, _cache));
+ print_def("CONSTANTPOOL_BASE", sizeof(constantPoolOopDesc));
+ nl();
+ print_def("CP_OFFSET", in_bytes(constantPoolCacheOopDesc::base_offset()));
+ nl();
+ print_def("BASE_OFFSET_BYTE", arrayOopDesc::base_offset_in_bytes(T_BYTE));
+ print_def("BASE_OFFSET_SHORT", arrayOopDesc::base_offset_in_bytes(T_SHORT));
+ print_def("BASE_OFFSET_WORD", arrayOopDesc::base_offset_in_bytes(T_INT));
+ print_def("BASE_OFFSET_LONG", arrayOopDesc::base_offset_in_bytes(T_LONG));
  nl();
  print_def("SIZEOF_HANDLEMARK", sizeof(HandleMark));
 }
diff -ruNE old/icedtea6/ports/hotspot/src/cpu/zero/vm/bytecodes_arm.def new/icedtea6/ports/hotspot/src/cpu/zero/vm/bytecodes_arm.def
--- old/icedtea6/ports/hotspot/src/cpu/zero/vm/bytecodes_arm.def 2009-11-04 11:33:19.000000000 +0000
+++ new/icedtea6/ports/hotspot/src/cpu/zero/vm/bytecodes_arm.def 2009-11-04 11:41:01.000000000 +0000
@@ -521,7 +521,7 @@
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
  DISPATCH_NEXT
- ldr tmp1, [r3, #12]
+ ldr tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUT_STACK 0, tmp1
  DISPATCH_FINISH
@@ -541,7 +541,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #3
- ldr tmp2, [r3, #16]
+ ldr tmp2, [r3, #BASE_OFFSET_LONG]
  DISPATCH_NEXT
  ldr tmp1, [r3, #20]
  DISPATCH_NEXT
@@ -565,7 +565,7 @@
  DISPATCH_NEXT
  add r3, r3, r2
  DISPATCH_NEXT
- ldrsb tmp1, [r3, #12]
+ ldrsb tmp1, [r3, #BASE_OFFSET_BYTE]
  DISPATCH_NEXT
  PUT_STACK 0, tmp1
  DISPATCH_FINISH
@@ -586,7 +586,7 @@
  DISPATCH_NEXT
  add r3, r3, r2, lsl #1
  DISPATCH_NEXT
- ldrh tmp1, [r3, #12]
+ ldrh tmp1, [r3, #BASE_OFFSET_SHORT]
  DISPATCH_NEXT
  PUT_STACK 0, tmp1
  DISPATCH_FINISH
@@ -607,7 +607,7 @@
  DISPATCH_NEXT
  add r3, r3, r2, lsl #1
  DISPATCH_NEXT
- ldrsh tmp1, [r3, #12]
+ ldrsh tmp1, [r3, #BASE_OFFSET_SHORT]
  DISPATCH_NEXT
  PUT_STACK 0, tmp1
  DISPATCH_FINISH
@@ -742,7 +742,7 @@
  DISPATCH_NEXT
  add tmp1, tmp1, tmp2, lsl #2
  DISPATCH_NEXT
- str r3, [tmp1, #12]
+ str r3, [tmp1, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -758,7 +758,7 @@
  bcs array_bound_exception_jpc_1_tmp2
  DISPATCH_NEXT
  add tmp2, tmp1, tmp2, lsl #3
- str r1, [tmp2, #16]
+ str r1, [tmp2, #BASE_OFFSET_LONG]
  DISPATCH_NEXT
  DISPATCH_NEXT
  str r3, [tmp2, #20]
@@ -778,7 +778,7 @@
  DISPATCH_NEXT
  add tmp1, tmp1, tmp2
  DISPATCH_NEXT
- strb r3, [tmp1, #12]
+ strb r3, [tmp1, #BASE_OFFSET_BYTE]
  DISPATCH_FINISH
 }
 
@@ -795,7 +795,7 @@
  DISPATCH_NEXT
  add tmp1, tmp1, tmp2, lsl #1
  DISPATCH_NEXT
- strh r3, [tmp1, #12]
+ strh r3, [tmp1, #BASE_OFFSET_SHORT]
  DISPATCH_FINISH
 }
 
@@ -1994,7 +1994,7 @@
  ldr r3, [istate, #ISTATE_METHOD] @ method
  ldrb lr, [jpc, #1]
 
- ldr tmp1, [r3, #12] @ constants
+ ldr tmp1, [r3, #METHOD_CONSTANTS] @ constants
 
  DISPATCH_START \seq_len
 
@@ -2012,14 +2012,14 @@
  bne 1f
 
  add r3, tmp1, lr, lsl #2
- ldr r3, [r3, #32]
+ ldr r3, [r3, #CONSTANTPOOL_BASE]
  DISPATCH_NEXT
  PUSH r3
  DISPATCH_FINISH
 1:
  cmp r3, #JVM_CONSTANT_Class
  bne 2f
- add r0, tmp1, #32
+ add r0, tmp1, #CONSTANTPOOL_BASE
  ldr r0, [r0, lr, lsl #2]
  ldr r1, [r0, #60]
  PUSH r1
@@ -2051,7 +2051,7 @@
 
  ldr r3, [istate, #ISTATE_METHOD] @ method
  ldrb ip, [jpc, #2]
- ldr r2, [r3, #12] @ constants
+ ldr r2, [r3, #METHOD_CONSTANTS] @ constants
 
  DISPATCH_START \seq_len
 
@@ -2069,7 +2069,7 @@
  bne 1f
 
  add r3, r2, lr, lsl #2
- ldr r3, [r3, #32]
+ ldr r3, [r3, #CONSTANTPOOL_BASE]
  DISPATCH_NEXT
  DISPATCH_NEXT
  PUSH r3
@@ -2077,7 +2077,7 @@
 1:
  cmp r3, #JVM_CONSTANT_Class
  bne 2f
- add r0, r2, #32
+ add r0, r2, #CONSTANTPOOL_BASE
  ldr r0, [r0, lr, lsl #2]
  ldr r1, [r0, #60]
  PUSH r1
@@ -2109,7 +2109,7 @@
 
  ldr tmp1, [istate, #ISTATE_METHOD] @ method
  ldrb lr, [jpc, #2]
- ldr r2, [tmp1, #12] @ constants
+ ldr r2, [tmp1, #METHOD_CONSTANTS] @ constants
 
  DISPATCH_START \seq_len
 
@@ -2126,8 +2126,8 @@
  bne vm_fatal_error
 
  add tmp1, r2, r3, lsl #2
- ldr r3, [tmp1, #32]
- ldr tmp1, [tmp1, #36]
+ ldr r3, [tmp1, #CONSTANTPOOL_BASE]
+ ldr tmp1, [tmp1, #CONSTANTPOOL_BASE+4]
  DISPATCH_NEXT
  DISPATCH_NEXT
  PUSH r3, tmp1
@@ -3126,7 +3126,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2, lsl #2
- ldr lr, [r3, #12]
+ ldr lr, [r3, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3145,7 +3145,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2, lsl #2
- ldr lr, [r3, #12]
+ ldr lr, [r3, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3166,7 +3166,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2
- ldrsb lr, [r3, #12]
+ ldrsb lr, [r3, #BASE_OFFSET_BYTE]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3187,7 +3187,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2, lsl #1
- ldrh lr, [r3, #12]
+ ldrh lr, [r3, #BASE_OFFSET_SHORT]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3208,7 +3208,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2, lsl #1
- ldrsh lr, [r3, #12]
+ ldrsh lr, [r3, #BASE_OFFSET_SHORT]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3227,7 +3227,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2
- ldrsb lr, [r3, #12]
+ ldrsb lr, [r3, #BASE_OFFSET_BYTE]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3246,7 +3246,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2, lsl #1
- ldrh lr, [r3, #12]
+ ldrh lr, [r3, #BASE_OFFSET_SHORT]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3265,7 +3265,7 @@
  cmp r2, lr
  bcs array_bound_exception_jpc_1
  add r3, r3, r2, lsl #1
- ldrsh lr, [r3, #12]
+ ldrsh lr, [r3, #BASE_OFFSET_SHORT]
  DISPATCH_NEXT
  PUSH lr
  DISPATCH_FINISH
@@ -3289,7 +3289,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
- str tmp1, [r3, #12]
+ str tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -3309,7 +3309,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2
- strb tmp1, [r3, #12]
+ strb tmp1, [r3, #BASE_OFFSET_BYTE]
  DISPATCH_FINISH
 }
 
@@ -3329,7 +3329,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #1
- strh tmp1, [r3, #12]
+ strh tmp1, [r3, #BASE_OFFSET_SHORT]
  DISPATCH_FINISH
 }
 
@@ -3346,7 +3346,7 @@
  bcs array_bound_exception_jpc_1_r3
  DISPATCH_NEXT
  add tmp1, tmp1, r3, lsl #2
- str r2, [tmp1, #12]
+ str r2, [tmp1, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -3363,7 +3363,7 @@
  bcs array_bound_exception_jpc_1_r3
  DISPATCH_NEXT
  add tmp1, tmp1, r3
- strb r2, [tmp1, #12]
+ strb r2, [tmp1, #BASE_OFFSET_BYTE]
  DISPATCH_FINISH
 }
 
@@ -3380,7 +3380,7 @@
  bcs array_bound_exception_jpc_1_r3
  DISPATCH_NEXT
  add tmp1, tmp1, r3, lsl #1
- strh r2, [tmp1, #12]
+ strh r2, [tmp1, #BASE_OFFSET_SHORT]
  DISPATCH_FINISH
 }
 
@@ -4754,7 +4754,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_3_r3
  add lr, lr, r3, lsl #2
- ldr r3, [lr, #12]
+ ldr r3, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH r2, r3
  DISPATCH_FINISH
@@ -4775,7 +4775,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_2_r3
  add lr, lr, r3, lsl #2
- ldr r3, [lr, #12]
+ ldr r3, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH r2, r3
  DISPATCH_FINISH
@@ -4796,7 +4796,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_2_r3
  add lr, lr, r3, lsl #2
- ldr r3, [lr, #12]
+ ldr r3, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH r2, r3
  DISPATCH_FINISH
@@ -4814,7 +4814,7 @@
  bcs array_bound_exception_jpc_2
  add r3, r3, r2, lsl #2
  POP lr @ r2 = index, lr = arrayref
- ldr r2, [r3, #12]
+ ldr r2, [r3, #BASE_OFFSET_WORD]
  SW_NPC cmp lr, #0
  SW_NPC beq null_ptr_exception_jpc_1
 .abortentry44:
@@ -4823,7 +4823,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_1
  add lr, lr, r2, lsl #2
- ldr r2, [lr, #12]
+ ldr r2, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH r2
  DISPATCH_FINISH
@@ -4841,7 +4841,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_3_r3
  add lr, lr, r3, lsl #2
- ldr r3, [lr, #12]
+ ldr r3, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  str r3, [locals, -r2, lsl #2]
  DISPATCH_FINISH
@@ -4860,7 +4860,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_2_r3
  add lr, lr, r3, lsl #2
- ldr r3, [lr, #12]
+ ldr r3, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  str r3, [locals, r2, lsl #2]
  DISPATCH_FINISH
@@ -4876,7 +4876,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_2_r3
  add lr, lr, r3, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
 
  POP r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref
  SW_NPC cmp r3, #0
@@ -4888,7 +4888,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
- str tmp1, [r3, #12]
+ str tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -4902,7 +4902,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_2_r3
  add lr, lr, r3, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
 
  POP r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref
  SW_NPC cmp r3, #0
@@ -4914,7 +4914,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2
- strb tmp1, [r3, #12]
+ strb tmp1, [r3, #BASE_OFFSET_BYTE]
  DISPATCH_FINISH
 }
 
@@ -4928,7 +4928,7 @@
  cmp r3, tmp1
  bcs array_bound_exception_jpc_2_r3
  add lr, lr, r3, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
 
  POP r2, r3 @ tmp1 = value, r2 = index, r3 = arrayref
  SW_NPC cmp r3, #0
@@ -4940,7 +4940,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #1
- strh tmp1, [r3, #12]
+ strh tmp1, [r3, #BASE_OFFSET_BYTE]
  DISPATCH_FINISH
 }
 
@@ -4955,7 +4955,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_2
  add r3, r3, r2, lsl #2
- ldr tmp1, [r3, #12] @ tmp1 = tos
+ ldr tmp1, [r3, #BASE_OFFSET_WORD] @ tmp1 = tos
  POP r2 @ r2 = tosm1
  DISPATCH_NEXT
  and tmp1, r2, tmp1 @ tosm1 <dop> tos
@@ -4974,7 +4974,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_2
  add r3, r3, r2, lsl #2
- ldr tmp1, [r3, #12] @ tmp1 = tos
+ ldr tmp1, [r3, #BASE_OFFSET_WORD] @ tmp1 = tos
  POP r2 @ r2 = tosm1
  DISPATCH_NEXT
  orr tmp1, r2, tmp1 @ tosm1 <dop> tos
@@ -4993,7 +4993,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_2
  add r3, r3, r2, lsl #2
- ldr tmp1, [r3, #12] @ tmp1 = tos
+ ldr tmp1, [r3, #BASE_OFFSET_WORD] @ tmp1 = tos
  POP r2 @ r2 = tosm1
  DISPATCH_NEXT
  eor tmp1, r2, tmp1 @ tosm1 <dop> tos
@@ -5012,7 +5012,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r3, [r3, #12] @ r1 = tos
+ ldr r3, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
         ldrsb   r1, [jpc, #2]
         ldrb    ip, [jpc, #3]
@@ -5035,7 +5035,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r3, [r3, #12] @ r1 = tos
+ ldr r3, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
         ldrsb   r1, [jpc, #2]
         ldrb    ip, [jpc, #3]
@@ -5058,7 +5058,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r3, [r3, #12] @ r1 = tos
+ ldr r3, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
         ldrsb   r1, [jpc, #2]
         ldrb    ip, [jpc, #3]
@@ -5081,7 +5081,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r3, [r3, #12] @ r1 = tos
+ ldr r3, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
         ldrsb   r1, [jpc, #2]
         ldrb    ip, [jpc, #3]
@@ -5104,7 +5104,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r3, [r3, #12] @ r1 = tos
+ ldr r3, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
         ldrsb   r1, [jpc, #2]
         ldrb    ip, [jpc, #3]
@@ -5127,7 +5127,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r3, [r3, #12] @ r1 = tos
+ ldr r3, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
         ldrsb   r1, [jpc, #2]
         ldrb    ip, [jpc, #3]
@@ -5150,7 +5150,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r2, [r3, #12] @ r1 = tos
+ ldr r2, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
  POP r3
         ldrsb   r1, [jpc, #2]
@@ -5174,7 +5174,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r2, [r3, #12] @ r1 = tos
+ ldr r2, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
  POP r3
         ldrsb   r1, [jpc, #2]
@@ -5198,7 +5198,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r2, [r3, #12] @ r1 = tos
+ ldr r2, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
  POP r3
         ldrsb   r1, [jpc, #2]
@@ -5222,7 +5222,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r2, [r3, #12] @ r1 = tos
+ ldr r2, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
  POP r3
         ldrsb   r1, [jpc, #2]
@@ -5246,7 +5246,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r2, [r3, #12] @ r1 = tos
+ ldr r2, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
  POP r3
         ldrsb   r1, [jpc, #2]
@@ -5270,7 +5270,7 @@
  cmp r2, r1
  bcs array_bound_exception_jpc_0
  add r3, r3, r2, lsl #2
- ldr r2, [r3, #12] @ r1 = tos
+ ldr r2, [r3, #BASE_OFFSET_WORD] @ r1 = tos
 
  POP r3
         ldrsb   r1, [jpc, #2]
@@ -5332,7 +5332,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_1
  add lr, lr, r2, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH tmp1
  DISPATCH_FINISH
@@ -5365,7 +5365,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
- str tmp1, [r3, #12]
+ str tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -5698,7 +5698,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_1
  add lr, lr, r2, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH tmp1
  DISPATCH_FINISH
@@ -5731,7 +5731,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
- str tmp1, [r3, #12]
+ str tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -6064,7 +6064,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_1
  add lr, lr, r2, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH tmp1
  DISPATCH_FINISH
@@ -6097,7 +6097,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
- str tmp1, [r3, #12]
+ str tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -6430,7 +6430,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_1
  add lr, lr, r2, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH tmp1
  DISPATCH_FINISH
@@ -6463,7 +6463,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
- str tmp1, [r3, #12]
+ str tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -6797,7 +6797,7 @@
  cmp r2, tmp1
  bcs array_bound_exception_jpc_1
  add lr, lr, r2, lsl #2
- ldr tmp1, [lr, #12]
+ ldr tmp1, [lr, #BASE_OFFSET_WORD]
  DISPATCH_NEXT
  PUSH tmp1
  DISPATCH_FINISH
@@ -6830,7 +6830,7 @@
  bcs array_bound_exception_jpc_1
  DISPATCH_NEXT
  add r3, r3, r2, lsl #2
- str tmp1, [r3, #12]
+ str tmp1, [r3, #BASE_OFFSET_WORD]
  DISPATCH_FINISH
 }
 
@@ -10032,7 +10032,7 @@
  DISPATCH_NEXT
  add tmp2, tmp1, tmp2, lsl #3
  fmacd d2, d1, d0
- vstr d2, [tmp2, #16]
+ vstr d2, [tmp2, #BASE_OFFSET_LONG]
  DISPATCH_NEXT
  DISPATCH_NEXT
  add stack, stack, #32
diff -ruNE old/icedtea6/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S new/icedtea6/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S
--- old/icedtea6/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S 2009-11-04 11:33:19.000000000 +0000
+++ new/icedtea6/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S 2009-11-04 11:40:55.000000000 +0000
@@ -17,12 +17,28 @@
 
 #ifdef HOTSPOT_ASM
 
+#define ARMv4
+
 #ifdef SHARK
 #define USE_COMPILER
 #define DISABLE_NOTICE_SAFEPOINTS
 #endif
 
-#define ARMv4
+#ifdef USE_COMPILER
+
+#define MP_COMPILE_THRESHOLD    0x10000         // 65536 - must be a single MOV constant
+#define UP_COMPILE_THRESHOLD    0x30000         // 196608 - must be a single MOV constant
+
+#define MAX_FG_METHOD_SIZE      500
+
+#ifndef DISABLE_ON_STACK_REPLACEMENT
+#define ON_STACK_REPLACEMENT
+#endif
+#ifndef ENABLE_BG_COMP_ON_NON_MP
+#define DISABLE_BG_COMP_ON_NON_MP
+#endif
+
+#endif // USE_COMPILER
 
 #ifndef DISABLE_NOTICE_SAFEPOINTS
 #define NOTICE_SAFEPOINTS
@@ -51,8 +67,6 @@
 #define constpool r9
 #define arm_sp r13
 
-#define CP_OFFSET 16
-
 #define tmp_xxx r7
 #define tmp_yyy r5
 #define tmp_vvv r9
@@ -238,6 +252,25 @@
 #endif
  .endm
 
+@------------------------------------------------
+@ On stack replacement macro
+@ Usage:
+@       OSR     <compiler specific code>
+@------------------------------------------------
+        .macro  OSR     p1, p2, p3, p4
+#ifdef ON_STACK_REPLACEMENT
+  .ifnes "\p4", ""
+        \p1 \p2, \p3, \p4
+  .else
+    .ifnes "\p3", ""
+        \p1 \p2, \p3
+    .else
+        \p1 \p2
+    .endif
+  .endif
+#endif
+        .endm
+
  .macro Opcode label
  ALIGN_OPCODE
 do_\label:
@@ -2582,42 +2615,39 @@
  PUSH tmp2
  DISPATCH_FINISH
 
-@ ip = branch offset
-@ r0 = 1st bytecode
-@ jpc has been updated
  Opcode goto
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
+branch_taken:
         orr     tmp1, tmp1, r1, lsl #8
         DISPATCH_START_REG tmp1
-branch_taken:
- ldr r2, [dispatch, #SafePointSynchronize_state_Address-XXX]
  cmp tmp1, #0
+ ble do_backedge
+ DISPATCH_FINISH
+
+do_backedge:
   USEC ldr tmp2, [istate, #ISTATE_METHOD]
- ldr r1, [r2]
- bgt branch_no_check
+  OSR ldr lr, [dispatch, #InterpreterInvocationLimit_Address-XXX]
+  USEC ldr r1, [tmp2, #METHOD_BACKEDGECOUNTER]
+  USEC ldr ip, [tmp2, #METHOD_INVOCATIONCOUNTER]
+  USEC add r1, r1, #INVOCATIONCOUNTER_COUNTINCREMENT
+  OSR ldr lr, [lr]
+  USEC add ip, ip, #INVOCATIONCOUNTER_COUNTINCREMENT
+  USEC str r1, [tmp2, #METHOD_BACKEDGECOUNTER]
+  OSR cmp r1, lr, lsl #2
+  USEC str ip, [tmp2, #METHOD_INVOCATIONCOUNTER]
+  OSR bcs do_osr
 
-@ ECN: The C code does...
-@ if (UseCompiler && UseLoopCounter) {
-@ BACKEDGE_COUNT->increment();
-@ ...
-@ }
-@ However, I just increment the counter because the check is actually
-@ more expensive than the increment. I don't believe this matters
-@ semantically, since is UseCompiler or UseLoopCounter is false then
-@ we shouldn't even be looking at the backedge counter.
-@
-@ ECN: Concerns about counter overflowing
-@
-  USEC ldr r3, [tmp2, #METHOD_BACKEDGECOUNTER]
+osr_continue:
+ ldr ip, [dispatch, #SafePointSynchronize_state_Address-XXX]
+ ldr r1, [ip]
  cmp r1, #1
-  USEC add r3, r3, #INVOCATIONCOUNTER_COUNTINCREMENT
-  USEC str r3, [tmp2, #METHOD_BACKEDGECOUNTER]
-
- bne branch_no_check
+ beq do_synchronize
+ DISPATCH_STATE 1
+ DISPATCH_FINISH
 
- sub jpc, jpc, tmp1 @ Point jpc back at the branch!!!
 
+do_synchronize:
  add r0, istate, #ISTATE_THREAD
  bl HandleMarkCleanerD
  ldr r0, [istate, #ISTATE_THREAD]
@@ -2632,16 +2662,103 @@
  CACHE_JPC
  cmp r3, #0
  bne handle_exception
+ DISPATCH 0
+
+#ifdef ON_STACK_REPLACEMENT
+do_osr:
+ ldr ip, [dispatch, #UseOnStackReplacement_Address-XXX]
+ ldrb ip, [ip]
+ cmp ip, #0
+ beq osr_continue
+
+ ldr r3, [tmp2, #METHOD_CONSTMETHOD]
+ DECACHE_JPC
+ ldrh r3, [r3, #CONSTMETHOD_CODESIZE]
+ DECACHE_STACK
+ ldr r0, [istate, #ISTATE_THREAD]
+ sub r1, jpc, tmp1
+ cmp r3, #MAX_FG_METHOD_SIZE
+ bcc 1f
+ ldr tmp2, [dispatch, #BackgroundCompilation_Address-XXX]
+ mov r3, #1
+ ldr r5, [tmp2]
+ str r3, [tmp2]
+ bl _ZN18InterpreterRuntime26frequency_counter_overflowEP10JavaThreadPh
+ str r5, [tmp2]
+ b 2f
+1:
+ bl _ZN18InterpreterRuntime26frequency_counter_overflowEP10JavaThreadPh
+2:
+ ldr r3, [istate, #ISTATE_THREAD]
+ ASSERT_LOCALS_CACHED
+ ASSERT_STACK_CACHED
+ CACHE_CP
+ ldr r1, [r3, #THREAD_PENDING_EXC]
+ CACHE_JPC
+ cmp r1, #0
+ bne handle_exception
+ cmp r0, #0
+ beq 1f
+ ldr r1, [r0, #56]
+ cmn r1, #2
+ bne osr_migrate
+1:
+ DISPATCH_START 0
+ b osr_continue
+#endif
+
+#ifdef ON_STACK_REPLACEMENT
+osr_migrate:
+ ldr tmp1, [r0, #128] @ osr_method->osr_entry()
+ ldr tmp2, [istate, #ISTATE_ADVANCE_PC]
+@ ldr istate, [istate, #ISTATE_NEXT_FRAME]
+ mov r0, r3
+ bl _ZN13SharedRuntime19OSR_migration_beginEP10JavaThread
+ mov r1, r0
+ ldr r0, [istate, #ISTATE_METHOD]
+ ldrh lr, [r0, #METHOD_MAXLOCALS]
+ ldrh ip, [r0, #METHOD_SIZEOFPARAMETERS]
+ ldr r3, [istate, #ISTATE_THREAD]
+ sub lr, lr, ip
+ ldr r2, [r3, #THREAD_TOP_ZERO_FRAME]
+ add ip, r2, #4
+ ldr r2, [r2]
+ add ip, ip, lr, lsl #2
+ str r2, [r3, #THREAD_TOP_ZERO_FRAME]
+ str ip, [r3, #THREAD_JAVA_SP]
+ mov r2, tmp1
+; r0 = method
+; r1 = osr_buf
+; r2 = osr_entry
+ mov lr, pc
+ ldr pc, [tmp1]
+
+ cmp tmp2, #0
+ ldmeqfd arm_sp!, {regset, pc}
 
- DISPATCH_START_REG tmp1 @ Refetch opcode and update jpc again
-branch_no_check:
-@ ECN: There is no protection against INVOCATIONCOUNTER overflowing!!!
-  USEC ldr r3, [tmp2, #METHOD_INVOCATIONCOUNTER]
+ ldr istate, [istate, #ISTATE_NEXT_FRAME]
+        ldr lr, [istate, #-ISTATE_NEXT_FRAME+ISTATE_THREAD]!
+        CACHE_JPC
+        ldr     stack, [lr, #THREAD_JAVA_SP]
+        ldr     r2, [istate, #ISTATE_STACK_LIMIT]
+        sub     stack, stack, #4
+
+        ldr     r1, [lr, #THREAD_TOP_ZERO_FRAME]
+        add     r2, r2, #4
+        str     r2, [lr, #THREAD_JAVA_SP]
+        str     r1, [lr, #THREAD_LAST_JAVA_SP]
+        ldr     r3, [lr, #THREAD_PENDING_EXC]
+        DISPATCH_START_REG tmp2
+        CACHE_LOCALS
  DISPATCH_NEXT
-  USEC add r3, r3, #INVOCATIONCOUNTER_COUNTINCREMENT
  DISPATCH_NEXT
-  USEC str r3, [tmp2, #METHOD_INVOCATIONCOUNTER]
+        cmp     r3, #0
+        DISPATCH_NEXT
+        bne     return_exception
+ DISPATCH_NEXT
+        CACHE_CP
  DISPATCH_FINISH
+#endif
 
  Opcode ifeq
  Opcode ifnull
@@ -2649,11 +2766,8 @@
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, #0
-        orreq   tmp1, tmp1, r1, lsl #8
-        ldreqb  r0, [jpc, tmp1]!
-        ldrneb  r0, [jpc, #3]!
  beq branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode ifne
  Opcode ifnonnull
@@ -2661,55 +2775,40 @@
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, #0
-        orrne   tmp1, tmp1, r1, lsl #8
-        ldrneb  r0, [jpc, tmp1]!
-        ldreqb  r0, [jpc, #3]!
  bne branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode iflt
         POP     r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, #0
-        orrlt   tmp1, tmp1, r1, lsl #8
-        ldrltb  r0, [jpc, tmp1]!
-        ldrgeb  r0, [jpc, #3]!
  blt branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode ifge
         POP     r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, #0
-        orrge   tmp1, tmp1, r1, lsl #8
-        ldrgeb  r0, [jpc, tmp1]!
-        ldrltb  r0, [jpc, #3]!
  bge branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode ifgt
         POP     r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, #0
-        orrgt   tmp1, tmp1, r1, lsl #8
-        ldrgtb  r0, [jpc, tmp1]!
-        ldrleb  r0, [jpc, #3]!
  bgt branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode ifle
         POP     r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, #0
-        orrle   tmp1, tmp1, r1, lsl #8
-        ldrleb  r0, [jpc, tmp1]!
-        ldrgtb  r0, [jpc, #3]!
  ble branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode if_icmpeq
  Opcode if_acmpeq
@@ -2717,11 +2816,8 @@
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, r2
-        orreq   tmp1, tmp1, r1, lsl #8
-        ldreqb  r0, [jpc, tmp1]!
-        ldrneb  r0, [jpc, #3]!
  beq branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode if_icmpne
  Opcode if_acmpne
@@ -2729,55 +2825,40 @@
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, r2
-        orrne   tmp1, tmp1, r1, lsl #8
-        ldrneb  r0, [jpc, tmp1]!
-        ldreqb  r0, [jpc, #3]!
  bne branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode if_icmplt
         POP    r2, r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, r2
-        orrlt   tmp1, tmp1, r1, lsl #8
-        ldrltb  r0, [jpc, tmp1]!
-        ldrgeb  r0, [jpc, #3]!
  blt branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode if_icmpge
         POP    r2, r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, r2
-        orrge   tmp1, tmp1, r1, lsl #8
-        ldrgeb  r0, [jpc, tmp1]!
-        ldrltb  r0, [jpc, #3]!
  bge branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode if_icmpgt
         POP    r2, r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, r2
-        orrgt   tmp1, tmp1, r1, lsl #8
-        ldrgtb  r0, [jpc, tmp1]!
-        ldrleb  r0, [jpc, #3]!
  bgt branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode if_icmple
         POP    r2, r3
         ldrsb   r1, [jpc, #1]
         ldrb    tmp1, [jpc, #2]
         cmp     r3, r2
-        orrle   tmp1, tmp1, r1, lsl #8
-        ldrleb  r0, [jpc, tmp1]!
-        ldrgtb  r0, [jpc, #3]!
  ble branch_taken
- DISPATCH_BYTECODE
+ DISPATCH 3
 
  Opcode ireturn
  Opcode freturn
@@ -3122,7 +3203,7 @@
  cmpne r3, #JVM_CONSTANT_UnresolvedClass
  beq .new_slow_case
 
- add r3, lr, #32
+ add r3, lr, #CONSTANTPOOL_BASE
  ldr k_entry, [r3, r2, lsl #2]
 
  add r1, k_entry, #KLASS_PART
@@ -3308,7 +3389,7 @@
 4:
  ldr r0, [r0, #4]
  add r3, r3, tmp2, lsl #2
- ldr tmp1, [r3, #32]
+ ldr tmp1, [r3, #CONSTANTPOOL_BASE]
  cmp tmp1, r0
  beq .checkcast_exit
 
@@ -3401,7 +3482,7 @@
  cmp r0, #0
  ldr ip, [r3, #CONSTANTPOOL_TAGS]
  beq .instanceof_not_instance
- add ip, ip, #12
+ add ip, ip, #BASE_OFFSET_BYTE
  orr tmp2, r1, r2, lsl #8
  ldrb r2, [ip, tmp2]
  cmp r2, #JVM_CONSTANT_UnresolvedClassInError
@@ -3411,7 +3492,7 @@
 1:
  ldr r0, [r0, #4]
  add r3, r3, tmp2, lsl #2
- ldr tmp1, [r3, #32]
+ ldr tmp1, [r3, #CONSTANTPOOL_BASE]
  cmp tmp1, r0
  beq .instanceof_is_instance
 
@@ -3685,7 +3766,7 @@
  beq raise_exception
 .aastore_exit:
     ldr r2, [dispatch, #Universe_collectedHeap_Address-XXX]
- add r1, tmp1, #12
+ add r1, tmp1, #BASE_OFFSET_WORD
  str sl, [r1, tmp_vvv, asl #2]!
     ldr r3, [r2]
  mov lr, #0
@@ -4010,9 +4091,22 @@
 
 #ifdef USE_COMPILER
 sync_method_entry_freq_count_overflow:
+        ldr     r3, [r0, #METHOD_CONSTMETHOD]
+        ldrh    r3, [r3, #CONSTMETHOD_CODESIZE]
  mov r1, #0
  mov r0, tmp1
+        cmp     r3, #MAX_FG_METHOD_SIZE
+        bcc     1f
+        ldr     tmp2, [dispatch, #BackgroundCompilation_Address-XXX]
+        mov     r3, #1
+        ldr     r5, [tmp2]
+        str     r3, [tmp2]
+        bl      _ZN18InterpreterRuntime26frequency_counter_overflowEP10JavaThreadPh
+        str     r5, [tmp2]
+        b       2f
+1:
  bl _ZN18InterpreterRuntime26frequency_counter_overflowEP10JavaThreadPh
+2:
  ldr r0, [istate, #ISTATE_METHOD]
  CACHE_JPC
  ldr r3, [r0, #METHOD_ACCESSFLAGS]
@@ -4401,12 +4495,16 @@
  add r0, r0, ip
  add dispatch, r1, r0
 
+  USEC  ldr     r2, [r10, #METHOD_INVOCATIONCOUNTER]
+
  ldr stack, [tmp1, #THREAD_JAVA_SP]
 
  ldr r0, [tmp1, #THREAD_STACK_SIZE]
+  USEC  add     r2, r2, #INVOCATIONCOUNTER_COUNTINCREMENT * 4
  ldr r3, [tmp1, #THREAD_STACK_BASE]
  rsb r3, r0, r3
  rsb r3, r3, arm_sp
+  USEC  str     r2, [tmp2, #METHOD_INVOCATIONCOUNTER]
  cmp r3, #32768
  bge fast_normal_entry_with_len
 
@@ -4596,11 +4694,24 @@
  DISPATCH_FINISH
 #ifdef USE_COMPILER
 method_entry_freq_count_overflow:
+        ldr     r3, [r10, #METHOD_CONSTMETHOD]
  DECACHE_JPC
+        ldrh    r3, [r3, #CONSTMETHOD_CODESIZE]
  str r10, [istate, #ISTATE_METHOD]
  mov r1, #0
  mov r0, tmp1
+        cmp     r3, #MAX_FG_METHOD_SIZE
+        bcc     1f
+        ldr     tmp2, [dispatch, #BackgroundCompilation_Address-XXX]
+        mov     r3, #1
+        ldr     r5, [tmp2]
+        str     r3, [tmp2]
+        bl      _ZN18InterpreterRuntime26frequency_counter_overflowEP10JavaThreadPh
+        str     r5, [tmp2]
+        b       2f
+1:
  bl _ZN18InterpreterRuntime26frequency_counter_overflowEP10JavaThreadPh
+2:
  CACHE_JPC
  CACHE_CP
  DISPATCH 0
@@ -6230,12 +6341,14 @@
 
  ALIGN_CODE
 bci_init:
+        stmfd   sp!, {r4, lr}
+
  adrl r3, dispatch_init_adcon
  ldm r3, {r0, r1}
  add r0, r0, r3
- add r1, r1, r0
+        add     r4, r1, r0
  adrl r2, adcon_init_table
- mov r3, r1
+        mov     r1, r4
 1:
  ldr ip, [r2], #4
  cmp ip, #0
@@ -6244,12 +6357,37 @@
  bne 1b
  adrl r2, main_dispatch_table
  mov r1, #256
+        mov     r3, r4
 2:
  ldr ip, [r2], #4
  str ip, [r3], #4
  subs r1, r1, #1
  bne 2b
 
+#ifdef USE_COMPILER
+
+#define NPROCESSORS_CONF        83
+
+        mov     r0, #NPROCESSORS_CONF
+        bl      sysconf
+        cmp     r0, #2
+
+#ifdef DISABLE_BG_COMP_ON_NON_MP
+        movcc   r0, #0
+        ldrcc   r1, [r4, #BackgroundCompilation_Address-XXX]
+        strccb  r0, [r1]
+#endif
+
+        movcs   r0, #MP_COMPILE_THRESHOLD
+        movcc   r0, #UP_COMPILE_THRESHOLD
+        ldr     r1, [r4, #CompileThreshold_Address-XXX]
+        str     r0, [r1]
+
+
+#endif // USE_COMPILER
+
+        ldmfd   sp!, {r4, lr}
+
 #ifdef HW_FP
 vfp_init:
  stmfd sp!, {r4, r5, lr}
@@ -6349,6 +6487,9 @@
  .word _ZN11JvmtiExport28_can_post_interpreter_eventsE(GOT)
  .word UseCompiler(GOT)
  .word _ZN17InvocationCounter26InterpreterInvocationLimitE(GOT)
+        .word   CompileThreshold(GOT)
+        .word   BackgroundCompilation(GOT)
+        .word   UseOnStackReplacement(GOT)
  .word 0
 
  ALIGN_DATA
@@ -6628,9 +6769,14 @@
 CodeTrace_Buffer_Base:
  .space CODETRACE_BUFFER_SIZE
 #endif
+        .word   0, 0, 0, 0, 0, 0, 0, 0
+        .word   0, 0, 0, 0, 0
 DispatchBreakPoint: .word 0
 VFP_Flag: .word 0
 CodeTrace_Idx: .word 0
+UseOnStackReplacement_Address:                          .word   0
+BackgroundCompilation_Address:                          .word   0
+CompileThreshold_Address:                               .word   0
 InterpreterInvocationLimit_Address: .word 0
 UseCompiler_Address: .word 0
 can_post_interpreter_events: .word 0
diff -ruNE old/icedtea6/ports/hotspot/src/share/vm/shark/sharkCacheDecache.cpp new/icedtea6/ports/hotspot/src/share/vm/shark/sharkCacheDecache.cpp
--- old/icedtea6/ports/hotspot/src/share/vm/shark/sharkCacheDecache.cpp 2009-11-04 11:33:19.000000000 +0000
+++ new/icedtea6/ports/hotspot/src/share/vm/shark/sharkCacheDecache.cpp 2009-11-04 11:42:26.000000000 +0000
@@ -189,9 +189,6 @@
                                           int box_offset,
                                           int obj_offset)
 {
-  if (max_monitors() > 1)
-    Unimplemented();   // XXX which order will they be in?
-
   // Copy the monitor from the OSR buffer to the frame
   int src_offset = max_locals() + index * 2;
   builder()->CreateStore(

Re: Request to commit: HS16 + OSR changes for ARM

by Andrew Haley :: Rate this Message:

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Edward Nevill wrote:

> Hi Folks,
>
> The following changes make hs16 work for ARM and add OSR support for Shark. The files
> affected are
>
> - asm_helper.cpp
> - bytecodes_arm.def
> - cppInterpreter_arm.S
> - sharkCacheDecache.cpp
>
> The last change (sharkCacheDecache.cpp) is to fix an 'Unimplemented()' error when a
> method with multiple monitors is OSRed. I have discussed this change with Gary.
>
> Gary? Are you happy with the change to sharkCacheDecache.cpp?
>
> It has been suggested by Gary that if the changes are purely to ARM code then I should
> just commit. Andrew has said that he would prefer such changes were posted for
> discussion. Would it be a reasonable comproise to say that if the changes are posted,
> and there are no objections within 24 hours  then I can just go ahead and commit the changes
> (this would only apply to files which are ARM only).

That seems reasonable.

Andrew.

Re: Request to commit: HS16 + OSR changes for ARM

by Gary Benson :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

Edward Nevill wrote:

> The following changes make hs16 work for ARM and add OSR support for
> Shark. The files affected are
>
> - asm_helper.cpp
> - bytecodes_arm.def
> - cppInterpreter_arm.S
> - sharkCacheDecache.cpp
>
> The last change (sharkCacheDecache.cpp) is to fix an
> 'Unimplemented()' error when a method with multiple monitors is
> OSRed. I have discussed this change with Gary.
>
> Gary? Are you happy with the change to sharkCacheDecache.cpp?

I'm happy with the change -- I suggested it after all :) -- but
what's your status with the SCA?  Are your contributions covered?

Cheers,
Gary

--
http://gbenson.net/

Re: Request to commit: HS16 + OSR changes for ARM

by Xerxes Rånby :: Rate this Message:

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Edward Nevill skrev:

> Hi Folks,
>
> The following changes make hs16 work for ARM and add OSR support for Shark. The files
> affected are
>
> - asm_helper.cpp
> - bytecodes_arm.def
> - cppInterpreter_arm.S
> - sharkCacheDecache.cpp
>
> Regards,
> Ed.
>
>
> +#ifdef ON_STACK_REPLACEMENT
> +osr_migrate:
> + ldr tmp1, [r0, #128] @ osr_method->osr_entry()
> + ldr tmp2, [istate, #ISTATE_ADVANCE_PC]
> +@ ldr istate, [istate, #ISTATE_NEXT_FRAME]
> + mov r0, r3
> + bl _ZN13SharedRuntime19OSR_migration_beginEP10JavaThread
> + mov r1, r0
> + ldr r0, [istate, #ISTATE_METHOD]
> + ldrh lr, [r0, #METHOD_MAXLOCALS]
> + ldrh ip, [r0, #METHOD_SIZEOFPARAMETERS]
> + ldr r3, [istate, #ISTATE_THREAD]
> + sub lr, lr, ip
> + ldr r2, [r3, #THREAD_TOP_ZERO_FRAME]
> + add ip, r2, #4
> + ldr r2, [r2]
> + add ip, ip, lr, lsl #2
> + str r2, [r3, #THREAD_TOP_ZERO_FRAME]
> + str ip, [r3, #THREAD_JAVA_SP]
> + mov r2, tmp1
> +; r0 = method
> +; r1 = osr_buf
> +; r2 = osr_entry
> + mov lr, pc
> + ldr pc, [tmp1]
> +
> + cmp tmp2, #0
> + ldmeqfd arm_sp!, {regset, pc}
>  
Hi Edward!

I tried to build the regular hs14 with your patch applied and hit this
error while linking launcher.

Linking launcher...
/ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
undefined reference to `osr_buf'
/ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
undefined reference to `osr_entry'
/ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
undefined reference to `method'
collect2: ld returned 1 exit status
make[6]: *** [gamma] Error 1
make[6]: Leaving directory `

are the three lines

+; r0 = method
+; r1 = osr_buf
+; r2 = osr_entry

meant to be comments?


Cheers
Xerxes

Re: Request to commit: HS16 + OSR changes for ARM

by Xerxes Rånby :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

Xerxes Rånby skrev:

> Edward Nevill skrev:
>  
>> Hi Folks,
>>
>> The following changes make hs16 work for ARM and add OSR support for Shark. The files
>> affected are
>>
>> - asm_helper.cpp
>> - bytecodes_arm.def
>> - cppInterpreter_arm.S
>> - sharkCacheDecache.cpp
>>
>> Regards,
>> Ed.
>>
>>
>> +#ifdef ON_STACK_REPLACEMENT
>> +osr_migrate:
>> + ldr tmp1, [r0, #128] @ osr_method->osr_entry()
>> + ldr tmp2, [istate, #ISTATE_ADVANCE_PC]
>> +@ ldr istate, [istate, #ISTATE_NEXT_FRAME]
>> + mov r0, r3
>> + bl _ZN13SharedRuntime19OSR_migration_beginEP10JavaThread
>> + mov r1, r0
>> + ldr r0, [istate, #ISTATE_METHOD]
>> + ldrh lr, [r0, #METHOD_MAXLOCALS]
>> + ldrh ip, [r0, #METHOD_SIZEOFPARAMETERS]
>> + ldr r3, [istate, #ISTATE_THREAD]
>> + sub lr, lr, ip
>> + ldr r2, [r3, #THREAD_TOP_ZERO_FRAME]
>> + add ip, r2, #4
>> + ldr r2, [r2]
>> + add ip, ip, lr, lsl #2
>> + str r2, [r3, #THREAD_TOP_ZERO_FRAME]
>> + str ip, [r3, #THREAD_JAVA_SP]
>> + mov r2, tmp1
>> +; r0 = method
>> +; r1 = osr_buf
>> +; r2 = osr_entry
>> + mov lr, pc
>> + ldr pc, [tmp1]
>> +
>> + cmp tmp2, #0
>> + ldmeqfd arm_sp!, {regset, pc}
>>  
>>    
> Hi Edward!
>
> I tried to build the regular hs14 with your patch applied and hit this
> error while linking launcher.
>
> Linking launcher...
> /ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
> undefined reference to `osr_buf'
> /ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
> undefined reference to `osr_entry'
> /ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
> undefined reference to `method'
> collect2: ld returned 1 exit status
> make[6]: *** [gamma] Error 1
> make[6]: Leaving directory `
>
> are the three lines
>
> +; r0 = method
> +; r1 = osr_buf
> +; r2 = osr_entry
>
> meant to be comments?
>
>
> Cheers
> Xerxes
>  
My build linked sucessfully when i changed those three lines to @ comments

Xerxes

============= cut here
Index: icedtea6-tot/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S
===================================================================
---
icedtea6-tot.orig/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S  
2009-11-05 08:40:18.000000000 +0000
+++ icedtea6-tot/ports/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S  
2009-11-05 08:41:24.000000000 +0000
@@ -2727,9 +2727,9 @@
     str    r2, [r3, #THREAD_TOP_ZERO_FRAME]
     str    ip, [r3, #THREAD_JAVA_SP]
     mov    r2, tmp1
-; r0 = method
-; r1 = osr_buf
-; r2 = osr_entry
+@ r0 = method
+@ r1 = osr_buf
+@ r2 = osr_entry
     mov    lr, pc
     ldr    pc, [tmp1]
 


Parent Message unknown Re: Request to commit: HS16 + OSR changes for ARM

by Edward Nevill-3 :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

>> +; r0 = method
>> +; r1 = osr_buf
>> +; r2 = osr_entry
>> + mov lr, pc
>> + ldr pc, [tmp1]
>> +
>> + cmp tmp2, #0
>> + ldmeqfd arm_sp!, {regset, pc}
>>  
>Hi Edward!
>
>I tried to build the regular hs14 with your patch applied and hit this
>error while linking launcher.
>
>Linking launcher...
>/ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
>undefined reference to `osr_buf'
>/ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
>undefined reference to `osr_entry'
>/ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
>undefined reference to `method'
>collect2: ld returned 1 exit status
>make[6]: *** [gamma] Error 1
>make[6]: Leaving directory `
>
>are the three lines
>
>+; r0 = method
>+; r1 = osr_buf
>+; r2 = osr_entry
>

Yes, thanks for spotting this. A merge problem.

Other than this are you happy with the changes? I have successfully built hs14, hs16 & hs16 with Shark (with the above change applied).

Regards,
Ed.

Re: Request to commit: HS16 + OSR changes for ARM

by Xerxes Rånby :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

Edward Nevill skrev:

>>> +; r0 = method
>>> +; r1 = osr_buf
>>> +; r2 = osr_entry
>>> + mov lr, pc
>>> + ldr pc, [tmp1]
>>> +
>>> + cmp tmp2, #0
>>> + ldmeqfd arm_sp!, {regset, pc}
>>>  
>>>      
>> Hi Edward!
>>
>> I tried to build the regular hs14 with your patch applied and hit this
>> error while linking launcher.
>>
>> Linking launcher...
>> /ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
>> undefined reference to `osr_buf'
>> /ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
>> undefined reference to `osr_entry'
>> /ssd/icedtea6-tot-asm-shark/openjdk-ecj/build/linux-arm/hotspot/outputdir/linux_zero_shark/product/libjvm.so:
>> undefined reference to `method'
>> collect2: ld returned 1 exit status
>> make[6]: *** [gamma] Error 1
>> make[6]: Leaving directory `
>>
>> are the three lines
>>
>> +; r0 = method
>> +; r1 = osr_buf
>> +; r2 = osr_entry
>>
>>    
>
> Yes, thanks for spotting this. A merge problem.
>
> Other than this are you happy with the changes? I have successfully built hs14, hs16 & hs16 with Shark (with the above change applied).
>
> Regards,
> Ed.
>  
I am very happy with the changes, it solves all issues that I currently
know!
I would like to see it all commited into the icedtea6 trunk.

With best regards,
Xerxes


Re: Request to commit: HS16 + OSR changes for ARM

by Gary Benson :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

Xerxes Rånby wrote:
> Edward Nevill skrev:
> > Other than this are you happy with the changes? I have
> > successfully built hs14, hs16 & hs16 with Shark (with the above
> > change applied).
>  
> I am very happy with the changes, it solves all issues that I
> currently know!
> I would like to see it all commited into the icedtea6 trunk.

Please do not commit the Shark change unless your contributions
are covered by the SCA.

Cheers,
Gary

--
http://gbenson.net/

Re: Request to commit: HS16 + OSR changes for ARM

by Matthias Klose-6 :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

On 05.11.2009 11:51, Gary Benson wrote:
> Please do not commit the Shark change unless your contributions
> are covered by the SCA.

why not? commits to IcedTea never had the precondition of SCA coverage. Is this
a policy change that I did miss?

  Matthias

Re: Request to commit: HS16 + OSR changes for ARM

by Xerxes Rånby :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

Gary Benson skrev:

> Xerxes Rånby wrote:
>  
>> Edward Nevill skrev:
>>    
>>> Other than this are you happy with the changes? I have
>>> successfully built hs14, hs16 & hs16 with Shark (with the above
>>> change applied).
>>>      
>>  
>> I am very happy with the changes, it solves all issues that I
>> currently know!
>> I would like to see it all commited into the icedtea6 trunk.
>>    
>
> Please do not commit the Shark change unless your contributions
> are covered by the SCA.
>
> Cheers,
> Gary
>
> --
> http://gbenson.net/
>  
I assumed Ed's statement from
http://mail.openjdk.java.net/pipermail/zero-dev/2009-July/000176.html
are still valid for these changes, Ed have anything changed reguarding
this matter?

"

BTW: I have signed the SCA so it is OK for any of these changes to be
checked into OpenJDK. ARM has disclaimed copyright interest as per
GPLv2 (although I have yet to get this in writing:-(). I have also
requested the JCK from Sun so hopefully should be in a positions to
verify it as Java Compliant.

Best Regards,
Ed.

"


At least i see no issues for you Gary to push these Shark changes upstream.

Cheers
Xerxes



Re: Request to commit: HS16 + OSR changes for ARM

by Mark Wielaard :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

On Thu, 2009-11-05 at 12:05 +0100, Matthias Klose wrote:
> commits to IcedTea never had the precondition of SCA coverage. Is this
> a policy change that I did miss?

Not that I know. IcedTea was specifically setup to be able to work on
code without legal politics (except for making sure the licenses used
are Free and compatible).


Re: Request to commit: HS16 + OSR changes for ARM

by Gary Benson :: Rate this Message:

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Matthias Klose wrote:
> On 05.11.2009 11:51, Gary Benson wrote:
> > Please do not commit the Shark change unless your contributions
> > are covered by the SCA.
>
> why not? commits to IcedTea never had the precondition of SCA
> coverage.  Is this a policy change that I did miss?

It's not an IcedTea policy, but ultimately the goal for Shark is to
get it upstream in much the same way as Zero now is, and I won't be
able to do that unless Shark is SCA clean.

Cheers,
Gary

--
http://gbenson.net/

Re: Request to commit: HS16 + OSR changes for ARM

by Gary Benson :: Rate this Message:

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Xerxes Rånby wrote:
> I assumed Ed's statement from
> http://mail.openjdk.java.net/pipermail/zero-dev/2009-July/000176.html
> are still valid for these changes, Ed have anything changed reguarding
> this matter?
>
> "BTW: I have signed the SCA so it is OK for any of these changes to
> be checked into OpenJDK. ARM has disclaimed copyright interest as
> per GPLv2 (although I have yet to get this in writing:-()."

Did you ever get it in writing Ed?

Cheers,
Gary

--
http://gbenson.net/

Parent Message unknown Re: Request to commit: HS16 + OSR changes for ARM

by Edward Nevill-3 :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

>Xerxes Rånby wrote:
>> I assumed Ed's statement from
>> http://mail.openjdk.java.net/pipermail/zero-dev/2009-July/000176.html
>> are still valid for these changes, Ed have anything changed reguarding
>> this matter?
>>
>> "BTW: I have signed the SCA so it is OK for any of these changes to
>> be checked into OpenJDK. ARM has disclaimed copyright interest as
>> per GPLv2 (although I have yet to get this in writing:-()."
>
>Did you ever get it in writing Ed?
>
>Cheers,
>Gary

No,

Regards,
Ed.

Re: Request to commit: HS16 + OSR changes for ARM

by Gary Benson :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

Edward Nevill wrote:

> >Xerxes R?nby wrote:
> > > I assumed Ed's statement from
> > > http://mail.openjdk.java.net/pipermail/zero-dev/2009-July/000176.html
> > > are still valid for these changes, Ed have anything changed
> > > reguarding this matter?
> > >
> > > "BTW: I have signed the SCA so it is OK for any of these changes
> > > to be checked into OpenJDK. ARM has disclaimed copyright
> > > interest as per GPLv2 (although I have yet to get this in
> > > writing:-()."
> >
> > Did you ever get it in writing Ed?
>
> No,

Ok.  I'm thinking that it shouldn't be an issue for this particular
Shark change, because you made it at my instruction.  I'm going to
ask that aph confirm my logic on that though, I'm not 100% sure how
all this works.  If it's not ok then I can always recreate it and
commit it myself.

Cheers,
Gary

--
http://gbenson.net/

Re: Request to commit: HS16 + OSR changes for ARM

by Gary Benson :: Rate this Message:

Reply to Author | View Threaded | Show Only this Message

Gary Benson wrote:

> Edward Nevill wrote:
> > > Xerxes R?nby wrote:
> > > > I assumed Ed's statement from
> > > > http://mail.openjdk.java.net/pipermail/zero-dev/2009-July/000176.html
> > > > are still valid for these changes, Ed have anything changed
> > > > reguarding this matter?
> > > >
> > > > "BTW: I have signed the SCA so it is OK for any of these
> > > > changes to be checked into OpenJDK. ARM has disclaimed
> > > > copyright interest as per GPLv2 (although I have yet to get
> > > > this in writing:-()."
> > >
> > > Did you ever get it in writing Ed?
> >
> > No,
>
> Ok.  I'm thinking that it shouldn't be an issue for this particular
> Shark change, because you made it at my instruction.  I'm going to
> ask that aph confirm my logic on that though, I'm not 100% sure how
> all this works.  If it's not ok then I can always recreate it and
> commit it myself.

It's not an issue for this change.  Ed, you have my approval.

Cheers,
Gary

--
http://gbenson.net/
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