Some MMU confusion

[wit-3]

Hi all,

I see the following code which is use to do the page lookup in the page
tables :

(_dtlb_miss_handler)
    l.addi    r3,r0,0xffffe000    // PAGE_MASK
//    l.j    d_pmd_bad
//    l.sw    0x0(r4),r0        // clear pmd

d_pmd_good:  
    /*
     * pte = *pte_offset(pmd, daddr);
     */
            l.lwz    r4,0x0(r4)        // get **pmd value
line1    l.and    r4,r4,r3        // & PAGE_MASK
            l.srli    r5,r2,0xd        // >> PAGE_SHIFT, r2 == EEAR
            l.andi    r3,r5,0x7ff        // (1UL << PAGE_SHIFT - 2) - 1
            l.slli    r3,r3,0x2        // to get address << 2
            l.add    r3,r3,r4
            l.lwz    r2,0x0(r3)        // this is pte at last
            /*
             * if (!pte_present(pte))
             */
            l.andi    r4,r2,0x1
            l.sfne    r4,r0            // is pte present
            l.bnf    d_pte_not_present
            l.addi    r3,r0,0xffffe3fa    // PAGE_MASK |
DTLB_UP_CONVERT_MASK

line1: r4 should have the pmd value in it at that time, and the OpenRisc
1000 Architecture Manual says the format of the page table entry looks like:

31:10            9                 8:6          5             4        
            3                  2               1         0
PPN            L(last)          PPI       Dirty      Accessed        
WOM         WBC          CI      CC

Here we should be going to get the start address of the level 2 page
table and store it in r4. But I don't understand why we're masking with
xffffe000.
Looks like PPN is a combination of CID (3bits) and Physical Frame Number
(19bits), are the CID bits the least significant bits in PPN?

Besides, I see a comment in code:
/* bit 4 is used in hardware as write back cache bit. we never use this bit
 * explicitly, so we can reuse it as _PAGE_FILE bit and mask it out when
 * writing into hardware pte's
 */
   
But in the architecture manual, the 5:0 bits are the same as the page
table entry format above, should it be bit 2 (or the third bit)?

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