Hi Willy,
> 1 - In the file "/kernel/src/arch/x86/mmu.h" : Calling the
> "flush_tlb(bool global)" function with "global" set to true will activate
> the global pages even if they are not. In fact, this function suppose that
> if "global" is set to true, the global page mechanism is active.
You seem to be right: At least for SMP, global pages can incorrectly be
enabled via flush_tlb(true). This should be fixed.
(In the non-SMP case, true is only passed when global pages are enabled
though this property is obfuscated by the configuration magic.)
> 2 - In the file "/kernel/src/arch/x86/x32/segdesc.h" : In lines 80 and
> 102, it is more logical to use 0xf in place of 0xff as the limit_high
> field is only 4 bits.
The whole masking is useless, but if it is done for clarity, it should mask
the correct number of bits using 0xf instead of the misleading 0xff.
So yes, you are right again.
> 3 - In the file "/kernel/src/arch/x86/segdesc.h" : In the
> "x86_descreg_t", why do you use the member
> "pad[sizeof(word_t)-sizeof(u16_t)]" in the union ? The GDTR and IDTR
> registers are 48 bits (address + limit) and the TR and LDTR registers are
> only 16 bits (selector) even if they are internally larger (the hidden
> part, only accessible by processor).
The padding seems to be both useless (as you pointed out) and wrong: If the
intention was to explicitly pad to full word width, pad should have type u8_t.
Using u16_t will add sizeof(word_t)-sizeof(u16_t) = 4-2 = 2 u16_t or one 32-bit
word (similar result for 64-bit word width).
The padding should probably be removed, we need to investigate this further.
Thank you for your feedback.
Kind regards,
Raphael
