Sourcing Older MPC555 CPUs

[cam13831]

Good Morning,

We are trying to source older MPC555 chips.  Specifically we are looking
for MPC555LFMZP40 with the K3 mask (Mask Set 6K02A, 1K83H, 3K83H,
5K83H).  We have tried several places and have had no luck and
unfortunately our current board layout does not allow us to do
modifications at this time to use the later M mask.

So I guess we were wondering if anyone would have any recommendations as
to where we might be able to find someone that would have a supply of
older stock (we are only looking for around 10 chips).

Thanks and have a great day.
Craig

[murphynetuk]

Hi,

I'm afraid I can't help you with sourcing K3 chips, but I'm curious as to the board layout differences required for the M mask chips?

I did a board design a few years ago which used the K3 chip, and if I need to change it I'd like to understand why...

Thanks, Ian


--- In MPC500@..., "cam13831" <cam13831@...> wrote:

>
>
> Good Morning,
>
> We are trying to source older MPC555 chips.  Specifically we are looking
> for MPC555LFMZP40 with the K3 mask (Mask Set 6K02A, 1K83H, 3K83H,
> 5K83H).  We have tried several places and have had no luck and
> unfortunately our current board layout does not allow us to do
> modifications at this time to use the later M mask.
>
> So I guess we were wondering if anyone would have any recommendations as
> to where we might be able to find someone that would have a supply of
> older stock (we are only looking for around 10 chips).
>
> Thanks and have a great day.
> Craig
>

[Dees Randy-rsaf30]

A properly designed system can use either the K3 or the M revisions of
the MPC555 without any issues.
 
however, there are errata fixes between the two mask sets that must be
accounted for in system designs.
 
of particular note: On the K3 mask set there were internal pull up
devices on some pins that could never be disabled. When software wrote
to the SPRDS bit in the PDMCR to disable these pull ups, they would not
be disabled. In revision M, they will be disabled. This affects the
following pins:  BI/STS, BURST, BDIP, TA, TS, TSIZ1, TSIZ0, TEA,
RD/WR,BR/VF1/IWP2, BG/VF0/IWP0, BB/VF2/IWP3. Depending on the
functionality enabled on the pin, this may or may not cause issues if
there is no external pull up. If the bus control pins (BB, BG, BR)
functions are enabled without pull ups, the bus will hang. for other
pins there are other conditions that could cause system failures. TEA
always requires an external resistor.
 
It should be noted that the internal weak devices are not specified to
guarantee correct operation if the external resistors are not designed
into the system. These external resistors are required per the MPC555
Reference Manual). K3 devices without these external resistors will work
properly in most cases, but will not be robust and could fail under some
conditions - like temperature or voltage extremes (within the normal
operating specifications of the device).
 
randy

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of murphynetuk
Sent: Sunday, June 14, 2009 4:02 AM
To: MPC500@...
Subject: [MPC500] Re: Sourcing Older MPC555 CPUs
 
Hi,

I'm afraid I can't help you with sourcing K3 chips, but I'm curious as
to the board layout differences required for the M mask chips?
 
I did a board design a few years ago which used the K3 chip, and if I
need to change it I'd like to understand why...
 


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