The Using watch dog in mcf52211

Dear all

Can some body help me to use watchdog in mcf52211. The register map in mcf5221x_reg.h does not include Backup watch dog registers.

Please send me the function for the same

Regards

Sanjay Morab

We have a MCF54450 running at a CPU CLK of 240Mhz. we are using U-Boot  1.2.0 our design is using 1 16 bit Flash a PC28F256P33B85 BGA64. We are executing code in Flash and have written a DDR-ram test walking ones and walking zeros and address and address this will run for days at a time billions and billions of writes and reads.

When we move this to DDR-ram which is a MICRON MT47H64M8CF-3:F which we use two of on SD-16 through SD-31with SD_A0-SD_A13 and

SD_CS

SD_DM2

SD_DQS2

SD_DM3

SD_DMQS3

We cannot run code we are using the same settings as the Reference design the same chips. I have layed out the board with mentor and have put restraints in all of the lines to keep them within .4 inches in length.

The symptoms are it either gets an exception out in space or locks up before it gets to NET: functions

Anyone have any thoughts about the issue.

Gregg

Hi all

More to report my actual problem appears to be cache I have disabled icache and u-boot seems to be working as expected. If I type (icache on) the system locks up. Anyone know if this symptom is telling me something I need to look at such a layout other variables ect.

Gregg

METRONICS /// 30 Harvey Road // Bedford, NH 03110-6818 / US

We have a MCF54450 running at a CPU CLK of 240Mhz. we are using U-Boot  1.2.0 our design is using 1 16 bit Flash a PC28F256P33B85 BGA64. We are executing code in Flash and have written a DDR-ram test walking ones and walking zeros and address and address this will run for days at a time billions and billions of writes and reads.

When we move this to DDR-ram which is a MICRON MT47H64M8CF-3:F which we use two of on SD-16 through SD-31with SD_A0-SD_A13 and

SD_CS

SD_DM2

SD_DQS2

SD_DM3

SD_DMQS3

We cannot run code we are using the same settings as the Reference design the same chips. I have layed out the board with mentor and have put restraints in all of the lines to keep them within .4 inches in length.

The symptoms are it either gets an exception out in space or locks up before it gets to NET: functions

Anyone have any thoughts about the issue.

Gregg

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Hi Gerry

This how we have them connected the only difference from our board and the reference design is that we have two less chips. We removed the chips that were connected to the SD_CS1 our burst mode is set at both ends to 8 I have tried 4 as well but then the SDRAM will not even function. Maybe you could pass this along to someone else if you need to if you need the code as well let me know what file or files.

Our basic problem is we cannot turn cache on and execute code with cache disabled everything works fine.

There seems to be an issue with polarity with the FB_TS line when using 16 bit as well. Looks to be the same issue that was on the original MCF5475 part. In our design we use the FB_TS line to latch the data into a LVCH162373 the problem arises at start up the TS line starts at reset as a high. This will not work because the address will not be latched until a low going signal. We could change the part to a LVCH162374 and it may work we chose to invert the signal. Very, very early MCF5475 had this problem and a lot of early reference design boards had this problem and were exchanged to have the processors replaced the applications notes were wrong as well. Basically one deficiency of the MCF54450 documentation is that no where do you show how to use a 16 bit muxed data bus part only 8 Bit.

Regards Gregg

METRONICS /// 30 Harvey Road // Bedford, NH 03110-6818 / US

Hey Greg,

Its gerry here!  I'm sorry I have not been able to reply, but I'm still without power! (since thursday!). Blackberies for once are coming in handy!


That aside,  when I read your original email, I was going to suggest turning off cache, as that will inhibit bursting. 

So, one thing you want to make sure still lines up on your design is that the correct lines are connected to the bank pins on the dram.  If not, the commands that are sent to the sdram registers inside of the sdram chip using the control lines will not be decoded correctly.  For example, when the burst length gets sent.

Go through all the bootup code for sdram, and make sure you can see that the commands are matchung up with with the correct lines on the sdram.  There is usually a table in the sdram datasheet which shows what combinations of control lines make up which command.

Not saying this is it, as I know you used the same part as us, but itou did mention that you have it connected differently.



----- Original Message -----
From: coldfire-bounce@... <coldfire-bounce@...>
To: Vahe Gerald-B06319
Sent: Wed Dec 17 09:19:09 2008
Subject: [ColdFire] RE: DDR ram issue using MCF54450 @240Mhz

Hi all



More to report my actual problem appears to be cache I have disabled icache and u-boot seems to be working as expected. If I type (icache on) the system locks up. Anyone know if this symptom is telling me something I need to look at such a layout other variables ect.



Gregg



________________________________

Gregg GRANVILLE

Hardware Engineering Manager

-------------------------------------------------------

Tel 1 603.622.0212 / Fax 1 603.623.5623

ggranville@... <ggranville@...>  / www.metronics.com <http://www.metronics.com>

-----------------------------------------------------------------------------------------

METRONICS /// 30 Harvey Road // Bedford, NH 03110-6818 / US

From: coldfire-bounce@... [coldfire-bounce@...] On Behalf Of Granville Gregg
Sent: Wednesday, December 17, 2008 8:00 AM
To: Granville Gregg
Subject: [ColdFire] DDR ram issue using MCF54450 @240Mhz



We have a MCF54450 running at a CPU CLK of 240Mhz. we are using U-Boot  1.2.0 our design is using 1 16 bit Flash a PC28F256P33B85 BGA64. We are executing code in Flash and have written a DDR-ram test walking ones and walking zeros and address and address this will run for days at a time billions and billions of writes and reads.

When we move this to DDR-ram which is a MICRON MT47H64M8CF-3:F which we use two of on SD-16 through SD-31with SD_A0-SD_A13 and

SD_CS

SD_DM2

SD_DQS2

SD_DM3

SD_DMQS3



We cannot run code we are using the same settings as the Reference design the same chips. I have layed out the board with mentor and have put restraints in all of the lines to keep them within .4 inches in length.



The symptoms are it either gets an exception out in space or locks up before it gets to NET: functions



Anyone have any thoughts about the issue.



Gregg





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I Just posted this on the Freescale support site as well anyone have any thoughts.

DDR2 Questions for the MCF54450VM240

I have separated my schematic to show 4 figures.  My basic problem is that I am unable to run the cache I am only using two chips they are what’s available from Micron today the evaluation board is using MT47H64M8CB-5E:B which are not availably any longer, on our board we are using MT47H64M8CF-3:F. We have written a DDR2 ram test this passes every time we then turn on cache and the system locks up. We are using uboot1.2 that came with the Development kit. Below is what our setting are for the EVB board.

Several people have responded to my questions on wildrice e-mail group that they thought the issue was burst mode and that I may have some lines wrong that is why I have included the Figures in the e-mail.

As you can see we have tried to recalculate the appropriate values for the registers with no luck.

#ifdef CL_3

#define CFG_SDRAM_CFG1     0x65311610 //rlb was 0x65311610 //IF CL==5 should be 0x67511610

#define CFG_SDRAM_CFG2     0x59670000 //rlb was 0x59670000 //if CL==5 should be 0x5B670000

#define CFG_SDRAM_MODE     0x00010033 //rlb was 0x00010033 //if CL==5 should be 0x00010053

#else //CL_5

#define CFG_SDRAM_CFG1      0x67511610 //rlb was 0x65311610 //IF CL==5 should be 0x67511610

#define CFG_SDRAM_CFG2      0x5B670000 //rlb was 0x59670000 //if CL==5 should be 0x5B670000

#define CFG_SDRAM_MODE   0x00010053 //rlb was 0x00010033 //if CL==5 should be 0x00010053

#endif //CL_3

There are 4 modifications to move the cas latency from 3 to 5.

RD_LAT in SDCFG1 changes from 3 to 5

SWT2RWP in SDCFG1 changes from 3 to 5

BWP2RWP in SDCFG2 changes from 9 to B

CL in DDR2 MODE REGISTER (SDMR) changes from 3 to 5

Could I get someone to help with getting these setting right for this DDR2 ram?

                                                                FIG 1

FIG 2

                                                                                FIG 3

                                                FIG 4

Gregg GRANVILLE

Hardware Engineering Manager

-------------------------------------

Tel 1 603.622.0212 / Fax 1 603.623.5623

ggranville@... / www.metronics.com

--------------------------------------------------------

METRONICS /// 30 Harvey Road // Bedford, NH 03110-6818 / US