Andreas Froese and I have finished a preview version of our verilog-A
(pure analogue) model generator.
The approach is based on the ngSpice-Model-generating script and
spice-wrapper.cc (github.com/gserdyuk/models-mot-adms), but we
streamlined this a bit and fixed several issues we had. some features
that might be of interest include:
- no need for spice-wrapper and spice hacks
- lots of probes to simplify debugging
- includes a simple first order opamp and hicum0 va model
- ac/dc/tr works in our examples.
Basically we have reduced the user interface to the following:
- admsXml(v2.3.0) must be installed
- configure should automatically find and make use of it
- after installation its as simple to use as:
$ $EDITOR dev.va
$ gnucap-adms dev.va
$ gcc -fPIC $(gnucap-conf --cppflags) --shared dev.cc -o dev.so
gnucap> load dev.so
I have merged this into a currently quite experimental branch (and
tagged 120327) which you can obtain with
git clone git://tool.em.cs.uni-frankfurt.de/git/gnucap --branch gnucap-uf
(installation following INSTALL should be straightforward).
there are several features and issues which you will like or not listed
in BUGS, TODO and CHANGES.uf. let me know how it breaks your favourite