disabling interrupts

[ranjith kumar-4]

Hi,

      How to disable interrupts on Pentium 4(or any
i386) machine?

I tried to include "cli" instruction in kernel module.
But got runtime errors.

Thanks in advance.



 
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[Attilio Rao-2]

2006/11/16, ranjith kumar <ranjith_kumar_b4u@...>:
> Hi,
>
>      How to disable interrupts on Pentium 4(or any
> i386) machine?
>
> I tried to include "cli" instruction in kernel module.
> But got runtime errors.
>
> Thanks in advance.

Why you want this?
Anyway, you can't disable interrupts for long periods of time, since
interrupts are required for a lot of vital works (i.e. pagefaults). In
this optic, even the "syscall handler" (exception handler of the int
0x80) is implemented through a trap gate more than an interrupt gate.
And keep in mind that a lot of kernel routines working on IF, preserve
the caller's eflags state (so disabling them would have no results in
some cases).

Attilio


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[ranjith kumar-4]

Hi,
    There are 4 types of prefetch instructions on
pentium 4 (IA-32) processor.
prefetchnta,prefetcht0,prefetcht1,prefetcht2.

In case of pentium 4, IA-32 otimization manuvals say
that prefetcht0,prefetcht1,prefetcht2 are identical.

It also says ONLY prefetchnta instruction prefetches
data into L2 cache without poluting caches.

 When all the four instructions prefetches data into
L2 cache (not into L1 cache) , what is the meaning in
saying prefetchnta does not polute caches?

ie)what is the difference between prefetchnta and
other instructions?


Thanks in advance.



 
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[Olivier Certner]

        Hi,

        On a pentium 4, prefetcht0, prefetcht1 and prefetch2 are identical, at least
if you don't have a level 3 cache. Intel's documentation is not very clear
about what happens with one more cache in the hierarchy.

        The prefetchnta instruction does the same thing (fetch some memory bytes into
the 2nd level cache) but it is supposed to fetch these bytes in only one way
of the cache. I don't know how the way is choosen. Unless you are trying to
fetch a relatively large volume of data or data with a special pattern (ie,
data that would be put at the same index in the cache, thus utilizing more
than one way), you won't see much difference from the prefetchtX variants.
You'll have to determine the characteristics of the L2 cache on your
paticular P4 processor target in order to check that.

                Olivier
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[Attilio Rao-2]

2006/12/6, ranjith kumar <ranjith_kumar_b4u@...>:

> Hi,
>     There are 4 types of prefetch instructions on
> pentium 4 (IA-32) processor.
> prefetchnta,prefetcht0,prefetcht1,prefetcht2.
>
> In case of pentium 4, IA-32 otimization manuvals say
> that prefetcht0,prefetcht1,prefetcht2 are identical.
>
> It also says ONLY prefetchnta instruction prefetches
> data into L2 cache without poluting caches.
>
>  When all the four instructions prefetches data into
> L2 cache (not into L1 cache) , what is the meaning in
> saying prefetchnta does not polute caches?
>
> ie)what is the difference between prefetchnta and
> other instructions?

First of all, it is important to say that prefetch* instruction is
only an hint for the CPU and not a *command* for that, so the CPU
needs to evaluate (in a not precisated way) if accept or not the
caching request.
>From this point of view, prefetch* instruction might be the more
accomodant possible for the CPU.
Different numbers mean different 'critical' level for the CPU (0 -
high critical, 2 - low critical), which means prefetching the cache
line to an higher level into the cache hierarchy.
This would means, in an hypotetical way:

prefetch0 -> L1 prefetching
prefetch1 -> L2 prefetching
prefetch2 -> L3 prefetching

And this is what really happens, for example, on P3 (if you consider
P3 has not L3 cache, prefetch2 == prefetch1).
On P4 things are different beacause you would not manipulate directly
L1 cache and, so, what happens is:

prefetch0 -> L2 prefetching
prefetch1 -> L2 prefetching
prefetch2 -> L3 prefetching
(if L3 cache is not present prefetch2 is the same as the other, from
this the assumption all the three instructions behave at the same).

prefetchnta is completely different beacause it fetches a cache line
into the NT cache structure.
Non Temporal caches are global caches which are particulary powerful
beacause they don't need of snooping messages between CPUs (and, in
this way, they reduce the CPUs<->caches traffic) and are used by NTI
family.

Attilio


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