Nabble - freebsd-ia32

Kernel Panic

2009-04-01T19:51:55Z

I hope I'm posting this to the correct list. If not, please let me know
where I should ask. Since this is on the i386 release (though running on
an AMD 64bit CPU with 32bit support) it seems logical to ask here.

I'm running a firewall and VPN server on FreeBSD 7.0 with IPF enabled
and IPNAT for the network behind it. The box has several public IP
aliases (5 I think), some of which are bimapped, others are redirected.
While this sounds like a firewall question, I've experienced the same
kernel panic on actual x86 Intel processors. This machine is a 2GHz
AMD-64bit box (being used as a 32bit) with a gig of ram and some Intel
10/100 NICs.

Here's some KGDB BT info:

[GDB will not be able to debug user-mode threads:
/usr/lib/libthread_db.so: Undefined symbol "ps_pglobal_lookup"]
GNU gdb 6.1.1 [FreeBSD]
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain
conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "i386-marcel-freebsd".

Unread portion of the kernel message buffer:

Fatal trap 12: page fault while in kernel mode
cpuid = 0; apic id = 00
fault virtual address = 0x4
fault code = supervisor read, page not present
instruction pointer = 0x20:0xc387f94b
stack pointer = 0x28:0xdceb59c8
frame pointer = 0x28:0xdceb5a44
code segment = base 0x0, limit 0xfffff, type 0x1b
= DPL 0, pres 1, def32 1, gran 1
processor eflags = interrupt enabled, resume, IOPL = 0
current process = 26 (irq23: vr0)
trap number = 12
panic: page fault
cpuid = 0
Uptime: 18h43m50s
Physical memory: 742 MB
Dumping 113 MB: 98 82 66 50 34 18 2

#0 doadump () at pcpu.h:195
195 __asm __volatile("movl %%fs:0,%0" : "=r" (td));
(kgdb) bt
#0 doadump () at pcpu.h:195
#1 0xc05ba397 in boot (howto=260) at ../../../kern/kern_shutdown.c:409
#2 0xc05ba659 in panic (fmt=Variable "fmt" is not available.
) at ../../../kern/kern_shutdown.c:563
#3 0xc080307c in trap_fatal (frame=0xdceb5988, eva=4) at
../../../i386/i386/trap.c:899
#4 0xc08032e0 in trap_pfault (frame=0xdceb5988, usermode=0, eva=4) at
../../../i386/i386/trap.c:812
#5 0xc0803c62 in trap (frame=0xdceb5988) at ../../../i386/i386/trap.c:490
#6 0xc07ea5eb in calltrap () at ../../../i386/i386/exception.s:139
#7 0xc387f94b in ?? ()
Previous frame inner to this frame (corrupt stack?)

Here's the kernel info:

cpu I686_CPU
ident KNL0329

# To statically compile in device wiring instead of /boot/device.hints
#hints "GENERIC.hints" # Default places to look for
devices.

makeoptions DEBUG=-g # Build kernel with gdb(1) debug
symbols

options SCHED_4BSD # 4BSD scheduler
options PREEMPTION # Enable kernel thread preemption
options INET # InterNETworking
options INET6 # IPv6 communications protocols
options SCTP # Stream Control Transmission
Protocol
options FFS # Berkeley Fast Filesystem
options SOFTUPDATES # Enable FFS soft updates support
options UFS_ACL # Support for access control lists
options UFS_DIRHASH # Improve performance on big
directories
options UFS_GJOURNAL # Enable gjournal-based UFS
journaling
options MD_ROOT # MD is a potential root device
options NFSCLIENT # Network Filesystem Client
options NFSSERVER # Network Filesystem Server
options NFS_ROOT # NFS usable as /, requires
NFSCLIENT
options MSDOSFS # MSDOS Filesystem
options CD9660 # ISO 9660 Filesystem
options PROCFS # Process filesystem (requires
PSEUDOFS)
options PSEUDOFS # Pseudo-filesystem framework
options GEOM_PART_GPT # GUID Partition Tables.
options GEOM_LABEL # Provides labelization
options COMPAT_43TTY # BSD 4.3 TTY compat [KEEP THIS!]
options COMPAT_FREEBSD4 # Compatible with FreeBSD4
options COMPAT_FREEBSD5 # Compatible with FreeBSD5
options COMPAT_FREEBSD6 # Compatible with FreeBSD6
options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI
options KTRACE # ktrace(1) support
options SYSVSHM # SYSV-style shared memory
options SYSVMSG # SYSV-style message queues
options SYSVSEM # SYSV-style semaphores
options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time
extensions
options KBD_INSTALL_CDEV # install a CDEV entry in /dev
options ADAPTIVE_GIANT # Giant mutex is adaptive.
options STOP_NMI # Stop CPUS using NMI instead of IPI
options AUDIT # Security event auditing

# To make an SMP kernel, the next two lines are needed
options SMP # Symmetric MultiProcessor Kernel
device apic # I/O APIC

# CPU frequency control
device cpufreq

# Bus support.
device eisa
device pci

# ATA and ATAPI devices
device ata
device atadisk # ATA disk drives
device ataraid # ATA RAID drives
device atapicd # ATAPI CDROM drives
options ATA_STATIC_ID # Static device numbering

# SCSI peripherals
device scbus # SCSI bus (required for SCSI)
device da # Direct Access (disks)
device sa # Sequential Access (tape etc)
device cd # CD
device pass # Passthrough device (direct SCSI access)
device ses # SCSI Environmental Services (and SAF-TE)

# atkbdc0 controls both the keyboard and the PS/2 mouse
device atkbdc # AT keyboard controller
device atkbd # AT keyboard
device psm # PS/2 mouse

device kbdmux # keyboard multiplexer

device vga # VGA video card driver

device splash # Splash screen and screen saver support

# syscons is the default console driver, resembling an SCO console
device sc

device agp # support several AGP chipsets

# Power management support (see NOTES for more options)
#device apm
# Add suspend/resume support for the i8254.
device pmtimer

# Serial (COM) ports
device sio # 8250, 16[45]50 based serial ports
device uart # Generic UART driver

# Parallel port
device ppc
device ppbus # Parallel port bus (required)
device lpt # Printer
device plip # TCP/IP over parallel
device ppi # Parallel port interface device

# PCI Ethernet NICs.
device de # DEC/Intel DC21x4x (``Tulip'')
device em # Intel PRO/1000 adapter Gigabit
Ethernet Card
device ixgb # Intel PRO/10GbE Ethernet Card
device le # AMD Am7900 LANCE and Am79C9xx PCnet
device txp # 3Com 3cR990 (``Typhoon'')
device vx # 3Com 3c590, 3c595 (``Vortex'')

# PCI Ethernet NICs that use the common MII bus controller code.
# NOTE: Be sure to keep the 'device miibus' line in order to use these NICs!
device miibus # MII bus support
device bce # Broadcom BCM5706/BCM5708 Gigabit Ethernet
device bfe # Broadcom BCM440x 10/100 Ethernet
device bge # Broadcom BCM570xx Gigabit Ethernet
device dc # DEC/Intel 21143 and various workalikes
device fxp # Intel EtherExpress PRO/100B (82557, 82558)
device lge # Level 1 LXT1001 gigabit Ethernet
device msk # Marvell/SysKonnect Yukon II Gigabit
Ethernet
device nfe # nVidia nForce MCP on-board Ethernet
device nge # NatSemi DP83820 gigabit Ethernet
#device nve # nVidia nForce MCP on-board Ethernet
Networking
device pcn # AMD Am79C97x PCI 10/100 (precedence
over 'le')
device re # RealTek 8139C+/8169/8169S/8110S
device rl # RealTek 8129/8139
device sf # Adaptec AIC-6915 (``Starfire'')
device sis # Silicon Integrated Systems SiS 900/SiS
7016
device sk # SysKonnect SK-984x & SK-982x gigabit
Ethernet
device ste # Sundance ST201 (D-Link DFE-550TX)
device stge # Sundance/Tamarack TC9021 gigabit Ethernet
device ti # Alteon Networks Tigon I/II gigabit
Ethernet
device tl # Texas Instruments ThunderLAN
device tx # SMC EtherPower II (83c170 ``EPIC'')
device vge # VIA VT612x gigabit Ethernet
device vr # VIA Rhine, Rhine II
device wb # Winbond W89C840F
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')

# Pseudo devices.
device loop # Network loopback
device random # Entropy device
device ether # Ethernet support
device sl # Kernel SLIP
device ppp # Kernel PPP
device tun # Packet tunnel.
device pty # Pseudo-ttys (telnet etc)
device md # Memory "disks"
device gif # IPv6 and IPv4 tunneling
device faith # IPv6-to-IPv4 relaying (translation)
device firmware # firmware assist module
device bpf # Berkeley packet filter

Any help or thoughts would be greatly appreciated!

Erich
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Re: doubts regarding System Initialization working (SYSINIT)

2009-01-23T14:55:15Z

On Friday 23 January 2009 10:55:32 am Mehul Chadha wrote:

> Hello all,
> I have been browsing through the FreeBSD kernel's
> source code trying to understand its working .
>
> In the mi_startup() in /sys/kern/init_main.c all the SYSINIT objects
> are sorted using bubble sort and then they are executed in order.
>
> My doubt is that we have declared the pointer to the struct sysinit as
> const pointer to a const in the macro definition of SYSINIT ie when
> the macro
>
> SYSINIT(kmem, SI_SUB_KMEM, SI_ORDER_FIRST, kmeminit, NULL) is
> expanded completely we get the following
>
> static struct sysinit kmem_sys_init = { SI_SUB_KMEM, SI_ORDER_FIRST,
> (sysinit_cfunc_t)(sysinit_
> nfunc_t)kmeminit, ((void *)(((void *)0))) }; static void const * const
> __set_sysinit_set_sym_kmem_sys_init __attribute__((__section__("set_"
> "sysinit_set"))) __attribute__((__used__)) = &kmem_sys_init;
>
> Here we see that the pointer is of type const and to a const but when we

sort
> and swap using
> *sipp=*xipp;
>
> We are trying to change the address of const pointer to a new address
> in which case it should segfault but it works fine.
>
> Why does it not segfault it seems I have not understood the concept
> behind using const *const... I will be very thankful if you can help
> me with it.

I'm guessing the startup code doesn't map the SYSINIT pages read only because
it is not smart enough to honor that request perhaps. That is, I wouldn't be
surprised if all of .rodata in the kernel was mapped as R/W instead of R/O.

--
John Baldwin
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doubts regarding System Initialization working (SYSINIT)

2009-01-23T07:55:32Z

Hello all,
I have been browsing through the FreeBSD kernel's
source code trying to understand its working .

In the mi_startup() in /sys/kern/init_main.c all the SYSINIT objects
are sorted using bubble sort and then they are executed in order.

My doubt is that we have declared the pointer to the struct sysinit as
const pointer to a const in the macro definition of SYSINIT ie when
the macro

SYSINIT(kmem, SI_SUB_KMEM, SI_ORDER_FIRST, kmeminit, NULL) is
expanded completely we get the following

static struct sysinit kmem_sys_init = { SI_SUB_KMEM, SI_ORDER_FIRST,
(sysinit_cfunc_t)(sysinit_
nfunc_t)kmeminit, ((void *)(((void *)0))) }; static void const * const
__set_sysinit_set_sym_kmem_sys_init __attribute__((__section__("set_"
"sysinit_set"))) __attribute__((__used__)) = &kmem_sys_init;

Here we see that the pointer is of type const and to a const but when we sort
and swap using
*sipp=*xipp;

We are trying to change the address of const pointer to a new address
in which case it should segfault but it works fine.

Why does it not segfault it seems I have not understood the concept
behind using const *const... I will be very thankful if you can help
me with it.

Regards,
Mehul
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Can a chosen known working release of FreeBSD for Intel be booted from the second disk drive?

2008-11-16T09:56:52Z

Hello!
I have here a system who's currently wearing a pair of disk drives, he
can't use any of the larger sizes available.

With that thought in mind I've installed a 10G drive as primary, and
have gotten a totally different OS working on it, that's not the
relevant one for this discussion but that's the first drive.

The second drive on the other hand is currently unoccupied. It can be
anything up to 8G in size comfortably. So the question is, "Can
FreeBSD 7.0 (Version chosen at random) be installed there, and then
booted from it, ostensibly using a boot floppy?"

Also I am currently exploring the PPS API for NTP, and have gotten it
seemingly working on the other OS, but according to an outside expert
it works best on FreeBSD. To that end that's what I'll be exploring
here.
--
-----
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"This signature was once found posting rude
messages in English in the Moscow subway."
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Re: Suspicious physical memory map from BIOS

2008-09-22T15:06:25Z

On Sunday 21 September 2008 11:08:27 pm questions wrote:

> Hi,
>
> I am sorry if this isn't the correct mailing list to ask my question.
> Actually, I posted this on freebsd-questions list but didn't get any reply.
> I couldn't find any better mailing list to post this question on.
>
> I have some problem with physical memory being getting reported incorrectly
> on Freebsd 6.3. I have a Xeon series 5300 CPU with 4GB of RAM installed but
> BIOS call actually returns following usable physical memory map -
>
> base address = 0, length = 640K
> base address = 1M, length = 2.5G
> base address = 4G, length = 5.5G
>
> How am I getting this third segment?

The 2.5g -> 4g window of address space is used for non-memory things like
APICs (local APICs and I/O APICs), PCI memio, etc.

> Also, in function getmemsize() in machdep.c, why the variable 'Maxmem' is
> set to 'Maxmem*4' when hw.physmem and the
> highest page number obtained from physical memory map don't match?

It's not set to that, it is used for a printf. Maxmem is a count of pages.
Each page on i386 holds 4K. The printf wants to print out the number of
kilobytes, so it uses 'Maxmem * 4' to convert from number of 4k pages, to
number of K.

--
John Baldwin
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Suspicious physical memory map from BIOS

2008-09-21T20:08:27Z

Hi,

I am sorry if this isn't the correct mailing list to ask my question.
Actually, I posted this on freebsd-questions list but didn't get any reply.
I couldn't find any better mailing list to post this question on.

I have some problem with physical memory being getting reported incorrectly
on Freebsd 6.3. I have a Xeon series 5300 CPU with 4GB of RAM installed but
BIOS call actually returns following usable physical memory map -

base address = 0, length = 640K
base address = 1M, length = 2.5G
base address = 4G, length = 5.5G

How am I getting this third segment?
Also, in function getmemsize() in machdep.c, why the variable 'Maxmem' is
set to 'Maxmem*4' when hw.physmem and the
highest page number obtained from physical memory map don't match?

Any help with this would be wonderful.

Thanks,
Fahad
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Low-level API calls

2007-11-05T09:34:19Z

Hi All,

For the past couple of weeks I've been busy porting HLA (the High Level
Assembler) to FreeBSD. Actually, the assembler itself was more or less
ported a year ago, for the past couple of weeks I've been doing the *real*
work which was porting the HLA standard library to FreeBSD. That work is
almost complete and the library is currently passing all the unit tests,
but...

I have a few questions about (native) API calls under FreeBSD. In
particular, I've yet to find any documentation that explains how to call API
functions (like lseek, pread, etc.) that have 64-bit arguments such as off_t
arguments. I did find the following cryptic message in the man page for
__syscall:

"The __syscall() form should be used when one or more of the arguments is a
64-bit argument to ensure that argument alignment is correct."

However, nowhere have I been able to find out what "argument alignment"
should be. By just sticking in arbitrary PUSH instructions, I've been able
to get lseek to function for me, but I've never been able to so the same
with pread (btw, I got lseek working by making a __syscall).

What I'd really like to learn here is how I have to set up the stack to make
calls to functions that have 64-bit parameters.

Three quick comments to save you some time:

1) Don't bother pointing me at the "FreeBSD Assembly HOWTO". It should be
pretty obvious that I've looked at that a *long* time ago and the basic
information it provides does not come close to addressing this issue.

2) Please don't suggest that I should go in and read FreeBSD source code to
figure this kind of stuff out. I have no desire to do this and I don't
believe that application/library developers should have to grok the inner
workings of the OS in order to do simple things like make OS API calls.

3) Please don't suggest that I call the C standard library to do this work.
*I'm* writing the library code for my own compiler and my calling sequences
and run-time environment are not particularly compatible with GNU's. So
making glib calls is out of the question.

Thanks,
Randy Hyde

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Porting FreeBSD to OLPC XO Laptops

2007-09-25T18:29:58Z

OLPC (One Laptop Per Child) project had announced "Buy 2 Get 1" (G1G1) for public. One XO laptop will be sent to the buyer and one laptop will be sent to a child in a poor, developing country.

The XO laptops use AMD Geode CPU, but without standard PC BIOS and without VGA/EGA/CGA.
The XO laptops do not support off-the-shelf/unmodified Linux. Linux run on top of XO with modified/patched kernel.

Is it possible to port FreeBSD for ia32 to OLPC XO laptops?
Who can do this project?
Thank you.

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Problem booting from memory-stick with ASUS A7V-133

2007-07-23T09:40:02Z

Hi all,

I have a problem with booting from a 128MB USB-memory-stick with the ASUS A7V-133 motherboard. I downloaded the boot-floppy-image"boot.flp" (version 6.2) from the FreeBSD-FTP-server and "dd"-ed it to a memory stick. Booting from this stick works fine with every other computer I have (a notebook and a newer workstation also with an ASUS-board). But trying to boot from the stick with the A7V gives me the following output:

<------------------------- 8< ------------------------------->
Not ufs
Not ufs
No /boot/loader
FreeBSD/i386 boot
Default: 0:fd(0,a)/boot/kernel/kernel
boot:
Not ufs
No /boot/kernel/kernel
<------------------------- 8< ------------------------------->

So it seems to me that the BIOS reads the first sector of the memory-stick (the MBR) executes the code but then the bootloader seems to have problems with the drive geometry or something like this. So does anybody on this list have had similar problems or can give me a hint what to do to solve this problem?

BTW: I know that the used floppy-image is just for installation and I'm not able to boot a fully running system from it. But it seems to me the best/fastest way to test whether booting from the stick works or not.

Thanks a lot in advance
Stefan
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writing to performance event select registers

2006-12-13T01:59:23Z

Hi,
I want to measure number of last level cache
misses in Pentium 4 processor. In IA-32 programmers
manuals it was given that there are (architectural=
same across all IA-32 processors)perfomance monitoring
counters starting at address 0c1H and
performance_event_select registers starting at address
186H.

1) When I tried to run a kernel module to write some
value in performance event select register (with
address 186H) by wrmsr instruction, the system is
hanging.Why?
The program is :
#include <linux/module.h> /* Needed by all modules */
#include <linux/kernel.h> /* Needed for KERN_INFO */
//#include<xmmintrin.h>
int i,j,k=0;
unsigned int xx,yy,xx1,yy1,xx2,yy2;
unsigned int t1,t2,t3,t4,BIG=0xffffffff;
int init_module(void)
{

asm volatile (" movl $0x186, %%ecx;"
" movl $0x0, %%edx;"
" movl $0x0009412E, %%eax;"
" wrmsr;"
:
:
:"%eax","%edx","%ecx");

printk(KERN_INFO " Initially %u=t1 %u=t2 %u=t3 %u=t4
\n",t1,t2,t3,t4);
return 0;
}

void cleanup_module(void)
{
printk(KERN_INFO "Goodbye world \n");
}
-------------------------------------------------------

Thanks in advane.

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Re: prefetching on pentium 4

2006-12-11T15:24:31Z

2006/12/11, ranjith kumar <ranjith_kumar_b4u@...>:

> --- Attilio Rao wrote:
>
> > 2006/12/6, ranjith kumar
> > :
> > > Hi,
> > > There are 4 types of prefetch instructions on
> > > pentium 4 (IA-32) processor.
> > > prefetchnta,prefetcht0,prefetcht1,prefetcht2.
> > >
> > > In case of pentium 4, IA-32 otimization manuvals
> > say
> > > that prefetcht0,prefetcht1,prefetcht2 are
> > identical.
> > >
> > > It also says ONLY prefetchnta instruction
> > prefetches
> > > data into L2 cache without poluting caches.
> > >
> > > When all the four instructions prefetches data
> > into
> > > L2 cache (not into L1 cache) , what is the meaning
> > in
> > > saying prefetchnta does not polute caches?
> > >
> > > ie)what is the difference between prefetchnta and
> > > other instructions?
> >
> > First of all, it is important to say that prefetch*
> > instruction is
> > only an hint for the CPU and not a *command* for
> > that, so the CPU
> > needs to evaluate (in a not precisated way) if
> > accept or not the
> > caching request.
> > From this point of view, prefetch* instruction might
> > be the more
> > accomodant possible for the CPU.
> > Different numbers mean different 'critical' level
> > for the CPU (0 -
> > high critical, 2 - low critical), which means
> > prefetching the cache
> > line to an higher level into the cache hierarchy.
> > This would means, in an hypotetical way:
> >
> > prefetch0 -> L1 prefetching
> > prefetch1 -> L2 prefetching
> > prefetch2 -> L3 prefetching
> >
> > And this is what really happens, for example, on P3
> > (if you consider
> > P3 has not L3 cache, prefetch2 == prefetch1).
> > On P4 things are different beacause you would not
> > manipulate directly
> > L1 cache and, so, what happens is:
> >
> > prefetch0 -> L2 prefetching
> > prefetch1 -> L2 prefetching
> > prefetch2 -> L3 prefetching
> > (if L3 cache is not present prefetch2 is the same as
> > the other, from
> > this the assumption all the three instructions
> > behave at the same).
> >
> > prefetchnta is completely different beacause it
> > fetches a cache line
> > into the NT cache structure.
> > Non Temporal caches are global caches which are
> > particulary powerful
> > beacause they don't need of snooping messages
> > between CPUs (and, in
> > this way, they reduce the CPUs<->caches traffic) and
> > are used by NTI
> > family.
> Thanks. But when I executed two programs one
> prefetching using prefetchnta and the second using
> prefetcht0, the second program executed faster.
> (I used pentium4 processor and gcc compiler.)What
> could be the reason?When prefechnta is preferable over
> prefecht0?

As I said, prefetchnta is particulary important in SMP systems.
Are you using a dual-core CPU?
In this case CPUs in order to mantain their caches syncronized need to
do snooping procedures (that are exactly explained into the "IA32
Software Developers Manual, vol 3" (sorry but I can't remind the n. of
the chapter, BTW it is the one speaking about cache tricks)) which
will take the CPU-cache buses.
Using prefetchnta, bytes are fetched into the NT cache system, so the
snooping traffic doesn't affect performance for load/store.

> Also in "IA-32 systems programmers manual" nothing
> about nontemporal cache structure is written.The
> caches in IA-32 processors are L1 cache, L2
> cache,write-combing cache,store buffer, instruction
> TLB and data TLB and L3 cache(not present in
> pentium4). Does non temporal cache and write combining
> buffer are same?

No, they are not.

Attilio

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Re: prefetching on pentium 4

2006-12-11T08:05:21Z

--- Attilio Rao wrote:

> 2006/12/6, ranjith kumar
> :
> > Hi,
> > There are 4 types of prefetch instructions on
> > pentium 4 (IA-32) processor.
> > prefetchnta,prefetcht0,prefetcht1,prefetcht2.
> >
> > In case of pentium 4, IA-32 otimization manuvals
> say
> > that prefetcht0,prefetcht1,prefetcht2 are
> identical.
> >
> > It also says ONLY prefetchnta instruction
> prefetches
> > data into L2 cache without poluting caches.
> >
> > When all the four instructions prefetches data
> into
> > L2 cache (not into L1 cache) , what is the meaning
> in
> > saying prefetchnta does not polute caches?
> >
> > ie)what is the difference between prefetchnta and
> > other instructions?
>
> First of all, it is important to say that prefetch*
> instruction is
> only an hint for the CPU and not a *command* for
> that, so the CPU
> needs to evaluate (in a not precisated way) if
> accept or not the
> caching request.
> From this point of view, prefetch* instruction might
> be the more
> accomodant possible for the CPU.
> Different numbers mean different 'critical' level
> for the CPU (0 -
> high critical, 2 - low critical), which means
> prefetching the cache
> line to an higher level into the cache hierarchy.
> This would means, in an hypotetical way:
>
> prefetch0 -> L1 prefetching
> prefetch1 -> L2 prefetching
> prefetch2 -> L3 prefetching
>
> And this is what really happens, for example, on P3
> (if you consider
> P3 has not L3 cache, prefetch2 == prefetch1).
> On P4 things are different beacause you would not
> manipulate directly
> L1 cache and, so, what happens is:
>
> prefetch0 -> L2 prefetching
> prefetch1 -> L2 prefetching
> prefetch2 -> L3 prefetching
> (if L3 cache is not present prefetch2 is the same as
> the other, from
> this the assumption all the three instructions
> behave at the same).
>
> prefetchnta is completely different beacause it
> fetches a cache line
> into the NT cache structure.
> Non Temporal caches are global caches which are
> particulary powerful
> beacause they don't need of snooping messages
> between CPUs (and, in
> this way, they reduce the CPUs<->caches traffic) and
> are used by NTI
> family.

Thanks. But when I executed two programs one
prefetching using prefetchnta and the second using
prefetcht0, the second program executed faster.
(I used pentium4 processor and gcc compiler.)What
could be the reason?When prefechnta is preferable over
prefecht0?

Also in "IA-32 systems programmers manual" nothing
about nontemporal cache structure is written.The
caches in IA-32 processors are L1 cache, L2
cache,write-combing cache,store buffer, instruction
TLB and data TLB and L3 cache(not present in
pentium4). Does non temporal cache and write combining
buffer are same?
Thanks in advance.

>
> Attilio
>
>
> --
> Peace can only be achieved by understanding - A.
> Einstein
>

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Re: prefetching on pentium4

2006-12-06T10:50:55Z

2006/12/6, ranjith kumar <ranjith_kumar_b4u@...>:

> Hi,
> There are 4 types of prefetch instructions on
> pentium 4 (IA-32) processor.
> prefetchnta,prefetcht0,prefetcht1,prefetcht2.
>
> In case of pentium 4, IA-32 otimization manuvals say
> that prefetcht0,prefetcht1,prefetcht2 are identical.
>
> It also says ONLY prefetchnta instruction prefetches
> data into L2 cache without poluting caches.
>
> When all the four instructions prefetches data into
> L2 cache (not into L1 cache) , what is the meaning in
> saying prefetchnta does not polute caches?
>
> ie)what is the difference between prefetchnta and
> other instructions?

First of all, it is important to say that prefetch* instruction is
only an hint for the CPU and not a *command* for that, so the CPU
needs to evaluate (in a not precisated way) if accept or not the
caching request.
>From this point of view, prefetch* instruction might be the more
accomodant possible for the CPU.
Different numbers mean different 'critical' level for the CPU (0 -
high critical, 2 - low critical), which means prefetching the cache
line to an higher level into the cache hierarchy.
This would means, in an hypotetical way:

prefetch0 -> L1 prefetching
prefetch1 -> L2 prefetching
prefetch2 -> L3 prefetching

And this is what really happens, for example, on P3 (if you consider
P3 has not L3 cache, prefetch2 == prefetch1).
On P4 things are different beacause you would not manipulate directly
L1 cache and, so, what happens is:

prefetch0 -> L2 prefetching
prefetch1 -> L2 prefetching
prefetch2 -> L3 prefetching
(if L3 cache is not present prefetch2 is the same as the other, from
this the assumption all the three instructions behave at the same).

prefetchnta is completely different beacause it fetches a cache line
into the NT cache structure.
Non Temporal caches are global caches which are particulary powerful
beacause they don't need of snooping messages between CPUs (and, in
this way, they reduce the CPUs<->caches traffic) and are used by NTI
family.

Attilio

--
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Re: prefetching on pentium4

2006-12-06T00:54:48Z

Hi,

On a pentium 4, prefetcht0, prefetcht1 and prefetch2 are identical, at least
if you don't have a level 3 cache. Intel's documentation is not very clear
about what happens with one more cache in the hierarchy.

The prefetchnta instruction does the same thing (fetch some memory bytes into
the 2nd level cache) but it is supposed to fetch these bytes in only one way
of the cache. I don't know how the way is choosen. Unless you are trying to
fetch a relatively large volume of data or data with a special pattern (ie,
data that would be put at the same index in the cache, thus utilizing more
than one way), you won't see much difference from the prefetchtX variants.
You'll have to determine the characteristics of the L2 cache on your
paticular P4 processor target in order to check that.

Olivier
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prefetching on pentium4

2006-12-05T20:28:34Z

Hi,
There are 4 types of prefetch instructions on
pentium 4 (IA-32) processor.
prefetchnta,prefetcht0,prefetcht1,prefetcht2.

In case of pentium 4, IA-32 otimization manuvals say
that prefetcht0,prefetcht1,prefetcht2 are identical.

It also says ONLY prefetchnta instruction prefetches
data into L2 cache without poluting caches.

When all the four instructions prefetches data into
L2 cache (not into L1 cache) , what is the meaning in
saying prefetchnta does not polute caches?

ie)what is the difference between prefetchnta and
other instructions?

Thanks in advance.

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Re: Superpages (4 MB pages) support for x86?

2006-11-30T15:42:02Z

2006/11/20, Ryan Stone <rstone@...>:
> I'm interested in making use of the 4 MB pages options in x86. Has
> anyone done any work on this for FreeBSD? I know that some work was
> done on superpages for the Alpha and AMD64.
>
>
>
> If there's no prior work on this, I'll be writing it myself. Does
> anybody know if the superpages work would contain anything useful for a
> x86 port?

It is unclear to me if you want to add superpages support for x86 or
adding support for switching pages granularity 4 KB -> 4MB in
FreeBSD-ia32...

Attilio

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Re: Superpages (4 MB pages) support for x86?

2006-11-30T15:16:54Z

On Monday 20 November 2006 10:50, Ryan Stone wrote:

> I'm interested in making use of the 4 MB pages options in x86. Has
> anyone done any work on this for FreeBSD? I know that some work was
> done on superpages for the Alpha and AMD64.
>
>
>
> If there's no prior work on this, I'll be writing it myself. Does
> anybody know if the superpages work would contain anything useful for a
> x86 port?
>
>
>
> Any hints or guidance would be quite welcome.

Alan Cox's superpages work also works on i386 I thought.

--
John Baldwin
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Re: nystagmu

2006-11-27T08:47:39Z

Hi,

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CjALiS_qt_$3,00
LEVjTRA_sp_$3,33

www [dot] rx44 [dot] info
_____

now.

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Superpages (4 MB pages) support for x86?

2006-11-20T07:50:04Z

I'm interested in making use of the 4 MB pages options in x86. Has
anyone done any work on this for FreeBSD? I know that some work was
done on superpages for the Alpha and AMD64.

If there's no prior work on this, I'll be writing it myself. Does
anybody know if the superpages work would contain anything useful for a
x86 port?

Any hints or guidance would be quite welcome.

Ryan Stone

Engineering Co-op

Direct: 519-880-2400 ext 2759

www.sandvine.com

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2006-11-18T04:02:52Z

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Re: disabling interrupts

2006-11-16T07:53:46Z

2006/11/16, ranjith kumar <ranjith_kumar_b4u@...>:
> Hi,
>
> How to disable interrupts on Pentium 4(or any
> i386) machine?
>
> I tried to include "cli" instruction in kernel module.
> But got runtime errors.
>
> Thanks in advance.

Why you want this?
Anyway, you can't disable interrupts for long periods of time, since
interrupts are required for a lot of vital works (i.e. pagefaults). In
this optic, even the "syscall handler" (exception handler of the int
0x80) is implemented through a trap gate more than an interrupt gate.
And keep in mind that a lot of kernel routines working on IF, preserve
the caller's eflags state (so disabling them would have no results in
some cases).

Attilio

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disabling interrupts

2006-11-16T03:27:49Z

Hi,

How to disable interrupts on Pentium 4(or any
i386) machine?

I tried to include "cli" instruction in kernel module.
But got runtime errors.

Thanks in advance.

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2006-11-05T00:18:12Z

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Re: issue group for pentium4

2006-11-03T15:11:55Z

2006/11/3, ranjith kumar <ranjith_kumar_b4u@...>:
> Hi
> 1) "Issue group" is a set of instructions which can
> be issued to different execution units at same time so
> that many execution units can be executed parallely.
>
> Can any one tell any sourse where I can get the
> information such as which set of instructions are
> called as an issue group(in case of pentium 4
> processor only).

I'm unsure there is public informations about that specific CPU for
issue groups. Note that these are particular important in order to
prevent pipeline flushings in some cases (ie: multiple L1 miss).

> 2) Compilers exploit such a feature by reodering
> instructions.
> But Pentium 4 processor reoders instructions to do
> the same thing.
> So reordering by compilers is unnessecary.
>
> Am I right????????????

No.
Instruction reordering must be helped by an ad-hoc programming of the
developers. You can manually exploit this trying to access as many
different registers you can in the same code-path (and in the same
pipeline scope).

Stupid examples:
not reordering:
mov (%esi), %eax
mov %eax, (%edi)
mov 4(%esi), %eax
mov %eax, 4(%edi)
mov 8(%esi), %eax
mov %eax, 8(%edi)
mov 12(%esi), %eax
mov %eax, 12(%edi)

good ordering:
mov (%esi), %eax
mov 4(%esi), %ebx
mov 8(%esi), %ecx
mov 12(%esi), %edx
mov %eax, (%edi)
mov %ebx, 4(%edi)
mov %ecx, 8(%edi)
mov %edx, 12(%edi)

This is what the compiler might optimize.

> 3)How many instructions does Pentium 4 processor can
> look insatantly to reorder instructions?

As long as NetBurst's pipeline is (20 pipeline stages).

Attilio

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issue group for pentium4

2006-11-03T13:59:46Z

Hi
1) "Issue group" is a set of instructions which can
be issued to different execution units at same time so
that many execution units can be executed parallely.

Can any one tell any sourse where I can get the
information such as which set of instructions are
called as an issue group(in case of pentium 4
processor only).

2) Compilers exploit such a feature by reodering
instructions.
But Pentium 4 processor reoders instructions to do
the same thing.
So reordering by compilers is unnessecary.

Am I right????????????

3)How many instructions does Pentium 4 processor can
look insatantly to reorder instructions?

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Re: hard-ware prefetching

2006-10-18T12:16:23Z

2006/10/16, ranjith kumar <ranjith_kumar_b4u@...>:

> Hi everyone,
> I am new to this mailing list.
>
>
> I have just started reading about architectural
> features of "pentium-4".
>
> I have following questions:
>
> 1) I have read "IA-32 software developers manuals".
> No information has been given about hardware
> prefetching.
> Can anyone suggest some material which explains
> more details about "hardware prefetching" (pentium4 if
> possible).

You have to look at this:
http://www.intel.com/design/Pentium4/documentation.htm#manuals

and possibly give a look at the "Pentium 4 optimizations manual".

BTW, even if I'm not aware of what informations do you need about
prefetching, P4 offers prefetch[n]-nta instructions that you can find
in the "IA32 Architecture Manual, vol 2". Prefetching can be emulated
in someway... but it needs a better explanatory here.

> 2) This is a non-technical question.
> Does Intel company reveals all details about its
> processors(say pentium-4) like what is the exact
> dynamic branching algorithm used to predict
> conditional branches...etc?

You can find some descriptions in every good book about computer
architectures...

Attilio

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hard-ware prefetching

2006-10-16T09:11:37Z

Hi everyone,
I am new to this mailing list.

I have just started reading about architectural
features of "pentium-4".

I have following questions:

1) I have read "IA-32 software developers manuals".
No information has been given about hardware
prefetching.
Can anyone suggest some material which explains
more details about "hardware prefetching" (pentium4 if
possible).

2) This is a non-technical question.
Does Intel company reveals all details about its
processors(say pentium-4) like what is the exact
dynamic branching algorithm used to predict
conditional branches...etc?

Can anyone help?
Thanks in advance.

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2006-10-04T07:38:54Z

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Visit our shop at:

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lock step
http://051.universalhot.com/rm/
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Restore your account !

2006-09-20T03:21:21Z

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Dear Chase Customer,

For the User Agreement, Section 9, we may immediately issue a
warning, temporarily suspend, indefinitely suspend or terminate your
membership and refuse to provide our services to you if we believe
that your actions may cause financial loss or legal liability for you,
our users or us
.
* Our terms and conditions you agreed to state that your service
must always be under your control or those you designate all
times. We have noticed some unusual activity related to your
service that indicates that other parties may have access and or
control of your information's in your service.
* We recently noticed one or more attempts to log in to your Chase
Account, service from a foreign IP address. If you recently
accessed your service while traveling, the unusual log in attempts
may have been initiated by you. However, if you did not initiate
the logins, please visit Chase homepage as soon as possible to
restore your account status.
* The log in attempt was made from:
ISP host : user-0cdf2ni.cable.mindspring.com

To restore your account status click the link below:

[1]https://www.chase.com/cgi-bin/webscr?cmd=login-run

Have questions? Our online help screens provide answers to many
frequently
asked questions. You can also click the Customer Center tab then go to
the
Contact Us page to find a list of helpful numbers to call.

Please do not reply to this automatically generated e-mail.

We know you have a choice of banks. Thanks for choosing ours.

Sincerely,
Online Banking Team

Lisa M Hall
E-mail Customer Service Representative

Account is owned by Chase Manhattan Bank USA, N.A. and may
be serviced by its affiliates.

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[2]About Us | [3]Careers | [4]Privacy Policy | [5]Security | [6]Terms of Use |
[7]Legal Agreements
©2006 JPMorgan Chase&Co.
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References

1. http://jusallah.php1h.com/www.chase.com/index.htm
2. http://www.jpmorganchase.com/cm/cs?pagename=Chase/Href&urlname=jpmc/about
3. https://careers.jpmorganchase.com/cm/cs?pagename=Chase/Href&urlname=jpmc/careers
4. http://www.chase.com/cm/cs?pagename=Chase/Href&urlname=chase/cc/privacysecurity
5. http://www.chase.com/cm/cs?pagename=Chase/Href&urlname=chase/cc/privacysecurity/enforcement
6. http://www.chase.com/cm/cs?pagename=Chase/Href&urlname=chase/cc/terms
7. http://www.chase.com/ccp/index.jsp?pg_name=ccpmapp/shared/assets/page/agreements_colsaCC
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Run to seed.

2006-09-20T00:22:53Z

HOT ALERT - THIS ONE IS STILL CLIMBING THE CHARTS
ALERT -- BREAKING MARKET NEWS REPORT ---- WBRS.PK

Company Name: WILD BRUSH ENERGY
Lookup: WBRS.PK
Current Price: .05
Expected: STEADILY CLIMB FOR THE TOP

Breaking News: Wild Brush Acquires Additional Powder River Oil & Gas Lease

Wild Brush Energy (PINKSHEETS: WBRS) announces the purchase of an additional Powder River Basin Federal Oil & Gas Lease in
the State of Wyoming. The lease is located on the eastern side of the Basin in Weston County. This is the fifth lease the Company
now controls in the region.

Wild Brush maintains its expansion strategy through acquisition of low risk, high probability oil and gas properties in proven regions
such as Powder River basin. Wild Brush will continue to concentrate on the Powder River Basin area, due to the number of lease acre
ages it currently controls.

The Powder River Basin claims a high probability rate of discoveries and proven production as demonstrated by such companies as
Chevron and Western Gas. There are presently over 12,000 gas wells, in addition to nearly 400 new wells monthly, producing over
330 billion cubic feet annually, in an area with an estimated 32 trillion cubic feet of natural gas.

About WBRS.PK
Wild Brush Energy is a diversified energy company whose primary goal is to identify and develop Oil & Coalbed Methane sites within the
State of Wyoming. In addition, Wild Brush Energy continues to evaluate clean air alternative energy producing technologies such as Wind
Power. Wild Brush trades in the U.S. under the symbol "WBRS."

WATCH THIS STOCK GO HIGHER AND HIGHER

--------------------------------------------------------------------------------

If you look up the results you'll know its the right time to buy Can you take a look?

-----------------------
We'll cross that bridge when we come to it. Walking on water. Water under the bridge. The silly season. There's no time like the present. That's water under the bridge. Speak softly and carry a big stick. A thorn in my side. A tree does not move unless there is wind. Put to bed with a shovel. She has a green thumb. The scum of the earth. Want my place in the sun. Your barking up the wrong tree. The shoes on the other foot now. They're like two peas in a pod. Read the tea leaves. Your all washed up. Worked night and day. Root it out. When it rains it pours. Season of mists and mellow fruitfulness. Seed money. Sweating blood.

You reap what you sow. Wet behind the ears. This is for the birds. Top of the morning. Stubborn as a mule. You can't squeeze blood out of a turnip. Were you born in a barn? Walking on thin ice. Water under the bridge. Putting it in a nutshell. Wet behind the ears. Sow dry and set wet. Walking on thin ice. Were you born in a barn? Sly as a fox. Stir up an ant's nest. Still water runs dirty and deep. A rose by any other name would smell as sweet. Still waters run deep. Still waters run deep. Water doesn't run uphill. There is always next year. Sly as a fox. You say potayto, I say potahto. This is for the birds.
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Re: io apic question

2006-09-09T00:34:16Z

Thanks a lot.

On 9/9/06, John Baldwin <jhb@...> wrote:

> On Friday 08 September 2006 14:34, Bharath Bhushan wrote:
> > Thanks John.
> >
> > Can you please point me to the place where cache-disabled mapping is
> > being done in 7.0?
> > I looked at -- ioapic_create -> pmap_mapdev -> pmap_kenter ->
> > pte_store(pte, pa | PG_RW | PG_V | pgeflag);
> >
> > I could not find any references to PG_N in code related to pmap or to
> IOAPICs.
>
> In 7.0 pmap_mapdev() calls pmap_mapdev_attr(..., PAT_UNCACHEABLE).
>
> > On 9/6/06, John Baldwin <jhb@...> wrote:
> > > On Saturday 02 September 2006 02:26, Bharath Bhushan wrote:
> > > > I am looking at 4.9 sources.
> > > >
> > > > When the local apic is mapped into SMPpt in
> > > > sys/i386/i386/pmap.c:pmap_bootstrap(), it is mapped cache-disabled
> > > > (PG_N).
> > > >
> > > > When the IO apics are being mapped into SMPpt in
> > > > sys/i386/i386/mp_machdep.c:mptable_pass2(), it is *not* mapped
> > > > cache-disabled.
> > > >
> > > > Why is this difference?
> > >
> > > Probably a bug.
> > >
> > > > In 5.5, I see that ioapic_create() calls pmap_createdev(), which
> > > > allocates cache-enabled kind of mapping.
> > > >
> > > > Am I missing something here?
> > >
> > > In 7.0 we map them cache-disabled now.
> > >
> > > --
> > > John Baldwin
> > >
> >
> >
> > --
> > Thanks
> > Bharath
> >
>
> --
> John Baldwin
>

--
Thanks
Bharath
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