hard-ware prefetching

[ranjith kumar-4]

Hi everyone,
             I am new to this mailing list.


I have just started reading about architectural
features of "pentium-4".

I have following questions:

1) I have read "IA-32 software developers manuals".
   No information has been given about hardware
prefetching.
   Can anyone suggest some material which explains
more details about "hardware prefetching" (pentium4 if
possible).

2) This is a non-technical question.
  Does Intel company reveals all details about its
processors(say pentium-4) like what is the exact
dynamic branching algorithm used to predict
conditional branches...etc?

Can anyone help?
Thanks in advance.

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[Attilio Rao-2]

2006/10/16, ranjith kumar <ranjith_kumar_b4u@...>:

> Hi everyone,
>             I am new to this mailing list.
>
>
> I have just started reading about architectural
> features of "pentium-4".
>
> I have following questions:
>
> 1) I have read "IA-32 software developers manuals".
>   No information has been given about hardware
> prefetching.
>   Can anyone suggest some material which explains
> more details about "hardware prefetching" (pentium4 if
> possible).

You have to look at this:
http://www.intel.com/design/Pentium4/documentation.htm#manuals

and possibly give a look at the "Pentium 4 optimizations manual".

BTW, even if I'm not aware of what informations do you need about
prefetching, P4 offers prefetch[n]-nta instructions that you can find
in the "IA32 Architecture Manual, vol 2". Prefetching can be emulated
in someway... but it needs a better explanatory here.

> 2) This is a non-technical question.
>  Does Intel company reveals all details about its
> processors(say pentium-4) like what is the exact
> dynamic branching algorithm used to predict
> conditional branches...etc?

You can find some descriptions in every good book about computer
architectures...

Attilio


--
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[ranjith kumar-4]

Hi
   1) "Issue group" is a set of instructions which can
be issued to different execution units at same time so
that many execution units can be executed parallely.

 Can any one tell any sourse where I can get the
information such as which set of instructions are
called as  an issue group(in case of pentium 4
processor only).                        

  2) Compilers exploit such a feature by reodering
instructions.
 But Pentium 4 processor reoders instructions to do
the same thing.
 So reordering by compilers is unnessecary.

Am I right????????????

3)How many instructions  does Pentium 4 processor can
look insatantly to reorder instructions?

 

 


 
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[Attilio Rao-2]

2006/11/3, ranjith kumar <ranjith_kumar_b4u@...>:
> Hi
>   1) "Issue group" is a set of instructions which can
> be issued to different execution units at same time so
> that many execution units can be executed parallely.
>
>  Can any one tell any sourse where I can get the
> information such as which set of instructions are
> called as  an issue group(in case of pentium 4
> processor only).

I'm unsure there is public informations about that specific CPU for
issue groups. Note that these are particular important in order to
prevent pipeline flushings in some cases (ie: multiple L1 miss).

>  2) Compilers exploit such a feature by reodering
> instructions.
>  But Pentium 4 processor reoders instructions to do
> the same thing.
>  So reordering by compilers is unnessecary.
>
> Am I right????????????

No.
Instruction reordering must be helped by an ad-hoc programming of the
developers. You can manually exploit this trying to access as many
different registers you can in the same code-path (and in the same
pipeline scope).

Stupid examples:
not reordering:
mov (%esi), %eax
mov %eax, (%edi)
mov 4(%esi), %eax
mov %eax, 4(%edi)
mov 8(%esi), %eax
mov %eax, 8(%edi)
mov 12(%esi), %eax
mov %eax, 12(%edi)

good ordering:
mov (%esi), %eax
mov 4(%esi), %ebx
mov 8(%esi), %ecx
mov 12(%esi), %edx
mov %eax, (%edi)
mov %ebx, 4(%edi)
mov %ecx, 8(%edi)
mov %edx, 12(%edi)

This is what the compiler might optimize.

> 3)How many instructions  does Pentium 4 processor can
> look insatantly to reorder instructions?

As long as NetBurst's pipeline is (20 pipeline stages).

Attilio


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