how to run hello world in on-chip ram?

[charlie yang]

hi all,  
I have a altera FPGA board with Cyclone II EP2c35 and synthesize the
orp_soc following the hardware tutorials. I have only one dedicated
JTAG for FPGA and have no  pins for or1k CPU. So I want to burn
the "hello world" program into on-chip ram by initializing this memory,
that is, let the JTAG download the all the CPU and program .
 so there are two questions for help:
  1) how to set start pointer of the reset.S and let the "hello world" run.
  2) I find the  hello.hex in or1k is incompatible with Intel hex format of
altera memory. how can I convert it to altera memory format?

Is there anybody using altera FPGA? Please give me some directions .
Thanks a lot !
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[Robert Cragie]

1) The CPU always vectors to 0x100 on reset so you will either need some
sort of bootstrap there or you will have to map RAM which you can download
to there.
2) You can always get to intelhex from the ELF file using:

or32-uclinux-objcopy -S -O ihex <ELFfile> <ihexfile>

Robert Cragie, Design Engineer
_______________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
http://www.jennic.com  Tel: [phone]
_______________________________________________________________

> -----Original Message-----
> From: openrisc-bounces@...
> [mailto:openrisc-bounces@...]On Behalf Of charlie yang
> Sent: 19 November 2007 04:17
> To: openrisc@...
> Subject: [openrisc] how to run hello world in on-chip ram?
>
>
> hi all,
> I have a altera FPGA board with Cyclone II EP2c35 and synthesize the
> orp_soc following the hardware tutorials. I have only one dedicated
> JTAG for FPGA and have no  pins for or1k CPU. So I want to burn
> the "hello world" program into on-chip ram by initializing this memory,
> that is, let the JTAG download the all the CPU and program .
>  so there are two questions for help:
>   1) how to set start pointer of the reset.S and let the "hello
> world" run.
>   2) I find the  hello.hex in or1k is incompatible with Intel hex
> format of
> altera memory. how can I convert it to altera memory format?
>
> Is there anybody using altera FPGA? Please give me some directions .
> Thanks a lot !
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc

_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[charlie yang]

  Thanks Robert.
  I use the or1k/hello-uart as my example.   use or32-uclinux-objcopy to
get a hello.hex and initialize the on-chip ram. When use modelsim to do
rtl simulation, I find the on-chip ram input address(wb_ss_adr_i)  repeat
like 0x100,0x000,0x104,0x00,0x100,0x000,0x104,0x000. and the ouput
data (wb_ss_dat_o)  is  always zero.
 
   In the hello-uart,  there is no FLASH,no Memory controller and no
cache. I don't know if my reset.S is incorrect or hex files is incorrect.
Please give me some hints. Thanks!

Here is my reset.S in hello-uart directory:
        .global ___main
        .section .stack  /*, "aw", @nobits*/
.space  STACK_SIZE
_stack:

        .section .vectors, "ax"
        .org 0x100
       
_reset_vector:
        l.nop
        l.nop
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0

        l.movhi r3,hi(SDRAM_BASE_ADDR)
        l.ori   r3,r3,lo(SDRAM_BASE_ADDR)
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
        .section .text

_start:
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2  
 
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.nop

___main:
        l.jr r9
        l.nop

Then I use the following step to generate hex file:
or32-uclinux-gcc -g -c -o reset.o reset.S
or32-uclinux-ld -Tram.ld -o hello.or32 reset.o hello.o
or32-uclinux-objcopy -O binary hello.or32 hello.bin
or32-uclinux-objcopy -S -O ihex hello.or32 hello.hex


----- Original Message -----
From: Robert Cragie<rcc@j...>
To:
Date: Mon Nov 19 09:24:52 CET 2007
Subject: [openrisc] how to run hello world in on-chip ram?

> 1) The CPU always vectors to 0x100 on reset so you will either need
> some
> sort of bootstrap there or you will have to map RAM which you can
> download
> to there.
> 2) You can always get to intelhex from the ELF file using:
> or32-uclinux-objcopy -S -O ihex <ELFfile> <ihexfile>
> Robert Cragie, Design Engineer
>
_____________________________________________________________
__
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> http://www.jennic.com Tel: [phone]
>
_____________________________________________________________
__

> > -----Original Message-----
> > From: openrisc-bounces at opencores.org
> > [mailto:openrisc-bounces at opencores.org]On Behalf Of charlie
> yang
> > Sent: 19 November 2007 04:17
> > To: openrisc at opencores.org
> > Subject: [openrisc] how to run hello world in on-chip ram?
> >
> >
> > hi all,
> > I have a altera FPGA board with Cyclone II EP2c35 and
> synthesize the
> > orp_soc following the hardware tutorials. I have only one
> dedicated
> > JTAG for FPGA and have no pins for or1k CPU. So I want to burn
> > the "hello world" program into on-chip ram by
> initializing this memory,
> > that is, let the JTAG download the all the CPU and program .
> > so there are two questions for help:
> > 1) how to set start pointer of the reset.S and let the
> "hello
> > world" run.
> > 2) I find the hello.hex in or1k is incompatible with Intel hex
> > format of
> > altera memory. how can I convert it to altera memory format?
> >
> > Is there anybody using altera FPGA? Please give me some
> directions .
> > Thanks a lot !
> > _______________________________________________
> > http://www.opencores.org/mailman/listinfo/openrisc 
>
>

_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[Robert Cragie]

It seems like you're not initialising your on chip RAM correctly, or it is
not configured correctly in your design as you'd expect to see 0x15000000
(l.nop) on the memory bus as it starts running. Are you offsetting by 0x100
correctly? Also, I'm not sure what SDRAM_BASE_ADDR points to either - you
may want to remove that part.

Robert Cragie, Design Engineer
_______________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
http://www.jennic.com  Tel: [phone]
_______________________________________________________________

> -----Original Message-----
> From: charlie yang [mailto:ydt@...]
> Sent: 20 November 2007 10:35
> To: rcc@...; openrisc@...
> Subject: Re: [openrisc] how to run hello world in on-chip ram?
>
>
>   Thanks Robert.
>
>   I use the or1k/hello-uart as my example.   use or32-uclinux-objcopy to
>
> get a hello.hex and initialize the on-chip ram. When use modelsim to do
>
> rtl simulation, I find the on-chip ram input address(wb_ss_adr_i)  repeat
>
> like 0x100,0x000,0x104,0x00,0x100,0x000,0x104,0x000. and the ouput
>
> data (wb_ss_dat_o)  is  always zero.
>
>
>
>    In the hello-uart,  there is no FLASH,no Memory controller and no
>
> cache. I don't know if my reset.S is incorrect or hex files is incorrect.
>
> Please give me some hints. Thanks!
>
>
>
> Here is my reset.S in hello-uart directory:
>
>         .global ___main
>
>         .section .stack  /*, "aw", @nobits*/
>
> .space  STACK_SIZE
>
> _stack:
>
>
>
>         .section .vectors, "ax"
>
>         .org 0x100
>
>
>
> _reset_vector:
>
>         l.nop
>
>         l.nop
>
>         l.addi  r2,r0,0x0
>
>         l.addi  r3,r0,0x0
>
>         l.addi  r4,r0,0x0
>
>         l.addi  r5,r0,0x0
>
>         l.addi  r6,r0,0x0
>
>         l.addi  r7,r0,0x0
>
>         l.addi  r8,r0,0x0
>
>         l.addi  r9,r0,0x0
>
>         l.addi  r10,r0,0x0
>
>         l.addi  r11,r0,0x0
>
>         l.addi  r12,r0,0x0
>
>         l.addi  r13,r0,0x0
>
>         l.addi  r14,r0,0x0
>
>         l.addi  r15,r0,0x0
>
>         l.addi  r16,r0,0x0
>
>         l.addi  r17,r0,0x0
>
>         l.addi  r18,r0,0x0
>
>         l.addi  r19,r0,0x0
>
>         l.addi  r20,r0,0x0
>
>         l.addi  r21,r0,0x0
>
>         l.addi  r22,r0,0x0
>
>         l.addi  r23,r0,0x0
>
>         l.addi  r24,r0,0x0
>
>         l.addi  r25,r0,0x0
>
>         l.addi  r26,r0,0x0
>
>         l.addi  r27,r0,0x0
>
>         l.addi  r28,r0,0x0
>
>         l.addi  r29,r0,0x0
>
>         l.addi  r30,r0,0x0
>
>         l.addi  r31,r0,0x0
>
>
>
>         l.movhi r3,hi(SDRAM_BASE_ADDR)
>
>         l.ori   r3,r3,lo(SDRAM_BASE_ADDR)
>
>         l.addi  r5,r0,0x00
>
>         l.sw    0(r3),r5
>
>         l.movhi r3,hi(_start)
>
>         l.ori   r3,r3,lo(_start)
>
>         l.jr    r3
>
>         l.nop
>
>         .section .text
>
>
>
> _start:
>
>         l.movhi r1,hi(_stack-4)
>
>         l.ori   r1,r1,lo(_stack-4)
>
>         l.addi  r2,r0,-3
>
>         l.and   r1,r1,r2
>
>
>
>         l.movhi r2,hi(_main)
>
>         l.ori   r2,r2,lo(_main)
>
>         l.jr    r2
>
>         l.nop
>
>
>
> ___main:
>
> l.jr r9
>
> l.nop
>
>
>
> Then I use the following step to generate hex file:
>
> or32-uclinux-gcc -g -c -o reset.o reset.S
>
> or32-uclinux-ld -Tram.ld -o hello.or32 reset.o hello.o
>
> or32-uclinux-objcopy -O binary hello.or32 hello.bin
>
> or32-uclinux-objcopy -S -O ihex hello.or32 hello.hex
>
>
>
>
>
> ----- Original Message -----
>
> From: Robert Cragie<rcc@j...>
>
> To:
>
> Date: Mon Nov 19 09:24:52 CET 2007
>
> Subject: [openrisc] how to run hello world in on-chip ram?
>
>
>
> > 1) The CPU always vectors to 0x100 on reset so you will either need
>
> > some
>
> > sort of bootstrap there or you will have to map RAM which you can
>
> > download
>
> > to there.
>
> > 2) You can always get to intelhex from the ELF file using:
>
> > or32-uclinux-objcopy -S -O ihex <ELFfile> <ihexfile>
>
> > Robert Cragie, Design Engineer
>
> >
>
> _____________________________________________________________
>
> __
>
> > Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
>
> > http://www.jennic.com Tel: [phone]
>
> >
>
> _____________________________________________________________
>
> __
>
> > > -----Original Message-----
>
> > > From: openrisc-bounces at opencores.org
>
> > > [mailto:openrisc-bounces at opencores.org]On Behalf Of charlie
>
> > yang
>
> > > Sent: 19 November 2007 04:17
>
> > > To: openrisc at opencores.org
>
> > > Subject: [openrisc] how to run hello world in on-chip ram?
>
> > >
>
> > >
>
> > > hi all,
>
> > > I have a altera FPGA board with Cyclone II EP2c35 and
>
> > synthesize the
>
> > > orp_soc following the hardware tutorials. I have only one
>
> > dedicated
>
> > > JTAG for FPGA and have no pins for or1k CPU. So I want to burn
>
> > > the "hello world" program into on-chip ram by
>
> > initializing this memory,
>
> > > that is, let the JTAG download the all the CPU and program .
>
> > > so there are two questions for help:
>
> > > 1) how to set start pointer of the reset.S and let the
>
> > "hello
>
> > > world" run.
>
> > > 2) I find the hello.hex in or1k is incompatible with Intel hex
>
> > > format of
>
> > > altera memory. how can I convert it to altera memory format?
>
> > >
>
> > > Is there anybody using altera FPGA? Please give me some
>
> > directions .
>
> > > Thanks a lot !
>
> > > _______________________________________________
>
> > > http://www.opencores.org/mailman/listinfo/openrisc
>
> >
>
> >

_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[charlie yang]

Hi,Roboert,

I don't know if the hello.hex is not suit for the altera ram. I use a single
port ram with 4kx32bit.  and set the ram.ld as:
MEMORY
        {
        vectors : ORIGIN = 0x00000000, LENGTH = 0x000000200
        ram     : ORIGIN = 0x000000200, LENGTH = 0x000000f00 -
0x0000200
        }
 when initializing the ram, i use the content offset to 0x100 in hello.hex
and cut the no useful information before address 0x100 ,which all is zero.

In simulation, Ithe pc value (equal to wb_ss_adr_i) vs wb_ss_dat_o is:
pc                  dat_o
0x000             15000000
0x100             9e000000
0x104             9e200000
0x108             9e400000
...
0x11c             9ee00000
0x120             Hiz   here cpu will report Starting exception: 7
utill pc run 128, pc will jump to 0x700 ,then 0x704, and will repeat
0x700,0x704 forever. the wb_ss_dat_o value is always 15000000.
what happen to this?

here is my chopped hello.hex:
:2000000015000000150000009C4000009C6000009C8000009CA000009CC
000009CE00000AE
:200020009D0000009D2000009D4000009D6000009D8000009DA000009DC
000009DE0000058
:200040009E0000009E2000009E4000009E6000009E8000009EA000009EC0
00009EE0000030
:200060009F0000009F2000009F4000009F6000009F8000009FA000009FC0
00009FE0000008
:2000800018200000A82135529C40FFFDE021100318400000A8422450440
010009C40000006
:2000A0004400480015000000000000000000000000000000000000000000
0000000000009F
:2000C0000000000000000000000000000000000000000000000000000000
00000000000020
:2000E0000000000000000000000000000000000000000000000000000000
00000000000000
:200100000000000000000000000000000000000000000000000000000000
000000000000DF
:200120000000000000000000000000000000000000000000000000000000
000000000000BF
:200140000000000000000000000000000000000000000000000000000000
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:200160000000000000000000000000000000000000000000000000000000
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:200180000000000000000000000000000000000000000000000000000000
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:2001A0000000000000000000000000000000000000000000000000000000
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:2001C0000000000000000000000000000000000000000000000000000000
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:2001E0000000000000000000000000000000000000000000000000000000
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:200200000000000000000000000000000000000000000000000000000000
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:200220000000000000000000000000000000000000000000000000000000
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----- Original Message -----
From: Robert Cragie<rcc@j...>
To:
Date: Tue Nov 20 12:27:57 CET 2007
Subject: [openrisc] how to run hello world in on-chip ram?

> It seems like you're not initialising your on chip RAM correctly,
> or it is
> not configured correctly in your design as you'd expect to see
> 0x15000000
> (l.nop) on the memory bus as it starts running. Are you offsetting
> by 0x100
> correctly? Also, I'm not sure what SDRAM_BASE_ADDR points to either
> - you
> may want to remove that part.
> Robert Cragie, Design Engineer
>

_____________________________________________________________
__
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> http://www.jennic.com Tel: [phone]
>
_____________________________________________________________
__

> > -----Original Message-----
> > From: charlie yang [mailto:ydt at ustc.edu]
> > Sent: 20 November 2007 10:35
> > To: rcc at jennic.com; openrisc at opencores.org
> > Subject: Re: [openrisc] how to run hello world in on-chip ram?
> >
> >
> > Thanks Robert.
> >
> > I use the or1k/hello-uart as my example. use
> or32-uclinux-objcopy to
> >
> > get a hello.hex and initialize the on-chip ram. When use
> modelsim to do
> >
> > rtl simulation, I find the on-chip ram input
> address(wb_ss_adr_i) repeat
> >
> > like 0x100,0x000,0x104,0x00,0x100,0x000,0x104,0x000. and the
> ouput
> >
> > data (wb_ss_dat_o) is always zero.
> >
> >
> >
> > In the hello-uart, there is no FLASH,no Memory controller and
> no
> >
> > cache. I don't know if my reset.S is incorrect or hex files is
> incorrect.
> >
> > Please give me some hints. Thanks!
> >
> >
> >
> > Here is my reset.S in hello-uart directory:
> >
> > .global ___main
> >
> > .section .stack /*, "aw", @nobits*/
> >
> > .space STACK_SIZE
> >
> > _stack:
> >
> >
> >
> > .section .vectors, "ax"
> >
> > .org 0x100
> >
> >
> >
> > _reset_vector:
> >
> > l.nop
> >
> > l.nop
> >
> > l.addi r2,r0,0x0
> >
> > l.addi r3,r0,0x0
> >
> > l.addi r4,r0,0x0
> >
> > l.addi r5,r0,0x0
> >
> > l.addi r6,r0,0x0
> >
> > l.addi r7,r0,0x0
> >
> > l.addi r8,r0,0x0
> >
> > l.addi r9,r0,0x0
> >
> > l.addi r10,r0,0x0
> >
> > l.addi r11,r0,0x0
> >
> > l.addi r12,r0,0x0
> >
> > l.addi r13,r0,0x0
> >
> > l.addi r14,r0,0x0
> >
> > l.addi r15,r0,0x0
> >
> > l.addi r16,r0,0x0
> >
> > l.addi r17,r0,0x0
> >
> > l.addi r18,r0,0x0
> >
> > l.addi r19,r0,0x0 > > l.addi r20,r0,0x0 > > l.addi
> r21,r0,0x0 > > l.addi r22,r0,0x0 > > l.addi r23,r0,0x0
> > > l.addi r24,r0,0x0 > > l.addi r25,r0,0x0 > >
> l.addi r26,r0,0x0 > > l.addi r27,r0,0x0 > > l.addi
> r28,r0,0x0 > > l.addi r29,r0,0x0 > > l.addi r30,r0,0x0
> > > l.addi r31,r0,0x0 > > > > l.movhi
> r3,hi(SDRAM_BASE_ADDR) > > l.ori r3,r3,lo(SDRAM_BASE_ADDR)
> > > l.addi r5,r0,0x00 > > l.sw 0(r3),r5 > >
> l.movhi r3,hi(_start) > > l.ori r3,r3,lo(_start) > >
> l.jr r3 > > l.nop > > .section .text > > >
> > _start: > > l.movhi r1,hi(_stack-4) > > l.ori
> r1,r1,lo(_stack-4) > > l.addi r2,r0,-3 > > l.and
> r1,r1,r2 > > > > l.movhi r2,hi(_main) > > l.ori
> r2,r2,lo(_main) > > l.jr r2 > > l.nop > > >
> > ___main: > > l.jr r9 > > l.nop > > >
> > Then I use the following step to generate hex file: > >
> or32-uclinux-gcc -g -c -o reset.o reset.S > > or32-uclinux-ld
> -Tram.ld -o hello.or32 reset.o hello.o > >
> or32-uclinux-objcopy -O binary hello.or32 hello.bin > >
> or32-uclinux-objcopy -S -O ihex hello.or32 hello.hex > > >
> > > > ----- Original Message ----- > > From: Robert
> Cragie<rcc at j...> > > To: > > Date: Mon Nov 19
> 09:24:52 CET 2007 > > Subject: [openrisc] how to run hello
> world in on-chip ram? > > > > > 1) The CPU always
> vectors to 0x100 on reset so you will either need > > >
> some > > > sort of bootstrap there or you will have to map
> RAM which you can > > > download > > > to there.
> > > > 2) You can always get to intelhex from the ELF file
> using: > > > or32-uclinux-objcopy -S -O ihex
> <ELFfile> <ihexfile> > > > Robert Cragie,
> Design Engineer > > > > >
>

_____________________________________________________________
 >
> > __ > > > Jennic Ltd, Furnival Street, Sheffield, S1
> 4QT, UK > > > http://www.jennic.com Tel: [phone]
> 2655 > > > > >
>
_____________________________________________________________
 >

> > __ > > > > -----Original Message----- > >
> > > From: openrisc-bounces at opencores.org > > >
> > [mailto:openrisc-bounces at opencores.org]On Behalf Of charlie
> > > > yang > > > > Sent: 19 November 2007
> 04:17 > > > > To: openrisc at opencores.org > >
> > > Subject: [openrisc] how to run hello world in on-chip
> ram? > > > > > > > > > > > > hi
> all, > > > > I have a altera FPGA board with Cyclone II
> EP2c35 and > > > synthesize the > > > >
> orp_soc following the hardware tutorials. I have only one > >
> > dedicated > > > > JTAG for FPGA and have no pins
> for or1k CPU. So I want to burn > > > > the "hello
> world" program into on-chip ram by > > > initializing
> this memory, > > > > that is, let the JTAG download the
> all the CPU and program . > > > > so there are two
> questions for help: > > > > 1) how to set start pointer
> of the reset.S and let the > > > "hello > >
> > > world" run. > > > > 2) I find the
> hello.hex in or1k is incompatible with Intel hex > > >
> > format of > > > > altera memory. how can I convert
> it to altera memory format? > > > > > > > >
> Is there anybody using altera FPGA? Please give me some > >
> > directions . > > > > Thanks a lot ! > > >
> > _______________________________________________ > > >
> > http://www.opencores.org/mailman/listinfo/openrisc > >
> > > > >
>

_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[Mark-28]

charlie yang wrote:
>  when initializing the ram, i use the content offset to 0x100 in hello.hex
> and cut the no useful information before address 0x100 ,which all is zero.
>
This was probably a mistake -- now the instructions that should be at
0x100 are at 0x000:

> In simulation, Ithe pc value (equal to wb_ss_adr_i) vs wb_ss_dat_o is:
> pc                  dat_o
> 0x000             15000000
> 0x100             9e000000
> 0x104             9e200000
> 0x108             9e400000

QED: you should have a NOP (i.e., 0x15000000) at 0x100, a NOP at 0x104,
etc. (q.v. the reset.S you posted previously).

>
> here is my chopped hello.hex:
> :2000000015000000150000009C4000009C6000009C8000009CA000009CC
> 000009CE00000AE
> :200020009D0000009D2000009D4000009D6000009D8000009DA000009DC
> 000009DE0000058
> :200040009E0000009E2000009E4000009E6000009E8000009EA000009EC0
> 00009EE0000030

You can plainly see how this maps to the outputs you describe above,
which suggests (to me, anyhow) that the memory is initialized correctly
but that the initialization file is incorrect (due to removing the data
from 0x000 to 0x100).
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[Robert Cragie]

Can you post the disassembly of your hello.or32 file?:

or32-uclinux-objdump -d hello.or32

That will give a clearer picture of where everything is.

Robert

Robert Cragie, Design Engineer
_______________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
http://www.jennic.com  Tel: [phone]
_______________________________________________________________

> -----Original Message-----
> From: openrisc-bounces@...
> [mailto:openrisc-bounces@...]On Behalf Of charlie yang
> Sent: 21 November 2007 11:57
> To: openrisc@...
> Subject: Re: [openrisc] how to run hello world in on-chip ram?
>
>
> Hi,Roboert,
>
> I don't know if the hello.hex is not suit for the altera ram. I
> use a single
> port ram with 4kx32bit.  and set the ram.ld as:
> MEMORY
>         {
>         vectors : ORIGIN = 0x00000000, LENGTH = 0x000000200
>         ram     : ORIGIN = 0x000000200, LENGTH = 0x000000f00 -
> 0x0000200
>         }
>  when initializing the ram, i use the content offset to 0x100 in
> hello.hex
> and cut the no useful information before address 0x100 ,which all is zero.
>
> In simulation, Ithe pc value (equal to wb_ss_adr_i) vs wb_ss_dat_o is:
> pc                  dat_o
> 0x000             15000000
> 0x100             9e000000
> 0x104             9e200000
> 0x108             9e400000
> ...
> 0x11c             9ee00000
> 0x120             Hiz   here cpu will report Starting exception: 7
> utill pc run 128, pc will jump to 0x700 ,then 0x704, and will repeat
> 0x700,0x704 forever. the wb_ss_dat_o value is always 15000000.
> what happen to this?
>
> here is my chopped hello.hex:
> :2000000015000000150000009C4000009C6000009C8000009CA000009CC
> 000009CE00000AE
> :200020009D0000009D2000009D4000009D6000009D8000009DA000009DC
> 000009DE0000058
> :200040009E0000009E2000009E4000009E6000009E8000009EA000009EC0
> 00009EE0000030
> :200060009F0000009F2000009F4000009F6000009F8000009FA000009FC0
> 00009FE0000008
> :2000800018200000A82135529C40FFFDE021100318400000A8422450440
> 010009C40000006
> :2000A0004400480015000000000000000000000000000000000000000000
> 0000000000009F
> :2000C0000000000000000000000000000000000000000000000000000000
> 00000000000020
> :2000E0000000000000000000000000000000000000000000000000000000
> 00000000000000
> :200100000000000000000000000000000000000000000000000000000000
> 000000000000DF
> :200120000000000000000000000000000000000000000000000000000000
> 000000000000BF
> :200140000000000000000000000000000000000000000000000000000000
> 0000000000009F
> :200160000000000000000000000000000000000000000000000000000000
> 0000000000007F
> :200180000000000000000000000000000000000000000000000000000000
> 0000000000005F
> :2001A0000000000000000000000000000000000000000000000000000000
> 0000000000003F
> :2001C0000000000000000000000000000000000000000000000000000000
> 0000000000001F
> :2001E0000000000000000000000000000000000000000000000000000000
> 000000000000FF
> :200200000000000000000000000000000000000000000000000000000000
> 000000000000DE
> :200220000000000000000000000000000000000000000000000000000000
> 000000000000BE
> :200240000000000000000000000000000000000000000000000000000000
> 0000000000009E
> :200260000000000000000000000000000000000000000000000000000000
> 0000000000007E
> :200280000000000000000000000000000000000000000000000000000000
> 0000000000005E
> :2002A0000000000000000000000000000000000000000000000000000000
> 0000000000003E
> :2002C0000000000000000000000000000000000000000000000000000000
> 0000000000001E
> :2002E0000000000000000000000000000000000000000000000000000000
> 000000000000FE
> :200300000000000000000000000000000000000000000000000000000000
> 000000000000DD
> :200320000000000000000000000000000000000000000000000000000000
> 000000000000BD
> :200340000000000000000000000000000000000000000000000000000000
> 0000000000009D
> :200360000000000000000000000000000000000000000000000000000000
> 0000000000007D
> :200380000000000000000000000000000000000000000000000000000000
> 0000000000005D
> :2003A0000000000000000000000000000000000000000000000000000000
> 0000000000003D
> :2003C0000000000000000000000000000000000000000000000000000000
> 0000000000001D
> :2003E0000000000000000000000000000000000000000000000000000000
> 000000000000FD
> :200400000000000000000000000000000000000000000000000000000000
> 000000000000DC
> :200420000000000000000000000000000000000000000000000000000000
> 000000000000BC
> :200440000000000000000000000000000000000000000000000000000000
> 0000000000009C
> :200460000000000000000000000000000000000000000000000000000000
> 0000000000007C
> :200480000000000000000000000000000000000000000000000000000000
> 0000000000005C
> :2004A0000000000000000000000000000000000000000000000000000000
> 0000000000003C
> :2004C0000000000000000000000000000000000000000000000000000000
> 0000000000001C
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> 000000000000FC
> :200500000000000000000000000000000000000000000000000000000000
> 000000000000DB
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> 000000000000BB
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> 0000000000009B
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> 0000000000007B
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> 0000000000005B
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> 0000000000003B
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> 0000000000001B
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> 000000000000FB
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> 000000000000DA
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> 000000000000BA
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> 0000000000009A
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> 0000000000005A
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> 000000000000FA
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> 000000000000D9
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> 00000000000099
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> 00000000000079
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> 00000000000059
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> 00000000000039
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> 00000000000019
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> 000000000000F9
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> 000000000000D8
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> 000000000000B8
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> 00000000000098
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> 00000000000078
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> 00000000000058
> :2008A0000000000000000000000000000000000000000000000000000000
> 00000000000038
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> 00000000000018
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> 000000000000F8
> :200900000000000000000000000000000000000000000000000000000000
> 000000000000D7
> :200920000000000000000000000000000000000000000000000000000000
> 000000000000B7
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> 00000000000097
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> 00000000000077
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> 00000000000057
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> 00000000000037
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> 00000000000017
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> 000000000000F7
> :200A00000000000000000000000000000000000000000000000000000000
> 000000000000D6
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> 000000000000B6
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> 00000000000096
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> 00000000000076
> :200A80000000000000000000000000000000000000000000000000000000
> 00000000000056
> :200AA0000000000000000000000000000000000000000000000000000000
> 00000000000036
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> 00000000000016
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>
>
>
> ----- Original Message -----
> From: Robert Cragie<rcc@j...>
> To:
> Date: Tue Nov 20 12:27:57 CET 2007
> Subject: [openrisc] how to run hello world in on-chip ram?
>
> > It seems like you're not initialising your on chip RAM correctly,
> > or it is
> > not configured correctly in your design as you'd expect to see
> > 0x15000000
> > (l.nop) on the memory bus as it starts running. Are you offsetting
> > by 0x100
> > correctly? Also, I'm not sure what SDRAM_BASE_ADDR points to either
> > - you
> > may want to remove that part.
> > Robert Cragie, Design Engineer
> >
> _____________________________________________________________
> __
> > Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> > http://www.jennic.com Tel: [phone]
> >
> _____________________________________________________________
> __
> > > -----Original Message-----
> > > From: charlie yang [mailto:ydt at ustc.edu]
> > > Sent: 20 November 2007 10:35
> > > To: rcc at jennic.com; openrisc at opencores.org
> > > Subject: Re: [openrisc] how to run hello world in on-chip ram?
> > >
> > >
> > > Thanks Robert.
> > >
> > > I use the or1k/hello-uart as my example. use
> > or32-uclinux-objcopy to
> > >
> > > get a hello.hex and initialize the on-chip ram. When use
> > modelsim to do
> > >
> > > rtl simulation, I find the on-chip ram input
> > address(wb_ss_adr_i) repeat
> > >
> > > like 0x100,0x000,0x104,0x00,0x100,0x000,0x104,0x000. and the
> > ouput
> > >
> > > data (wb_ss_dat_o) is always zero.
> > >
> > >
> > >
> > > In the hello-uart, there is no FLASH,no Memory controller and
> > no
> > >
> > > cache. I don't know if my reset.S is incorrect or hex files is
> > incorrect.
> > >
> > > Please give me some hints. Thanks!
> > >
> > >
> > >
> > > Here is my reset.S in hello-uart directory:
> > >
> > > .global ___main
> > >
> > > .section .stack /*, "aw", @nobits*/
> > >
> > > .space STACK_SIZE
> > >
> > > _stack:
> > >
> > >
> > >
> > > .section .vectors, "ax"
> > >
> > > .org 0x100
> > >
> > >
> > >
> > > _reset_vector:
> > >
> > > l.nop
> > >
> > > l.nop
> > >
> > > l.addi r2,r0,0x0
> > >
> > > l.addi r3,r0,0x0
> > >
> > > l.addi r4,r0,0x0
> > >
> > > l.addi r5,r0,0x0
> > >
> > > l.addi r6,r0,0x0
> > >
> > > l.addi r7,r0,0x0
> > >
> > > l.addi r8,r0,0x0
> > >
> > > l.addi r9,r0,0x0
> > >
> > > l.addi r10,r0,0x0
> > >
> > > l.addi r11,r0,0x0
> > >
> > > l.addi r12,r0,0x0
> > >
> > > l.addi r13,r0,0x0
> > >
> > > l.addi r14,r0,0x0
> > >
> > > l.addi r15,r0,0x0
> > >
> > > l.addi r16,r0,0x0
> > >
> > > l.addi r17,r0,0x0
> > >
> > > l.addi r18,r0,0x0
> > >
> > > l.addi r19,r0,0x0 > > l.addi r20,r0,0x0 > > l.addi
> > r21,r0,0x0 > > l.addi r22,r0,0x0 > > l.addi r23,r0,0x0
> > > > l.addi r24,r0,0x0 > > l.addi r25,r0,0x0 > >
> > l.addi r26,r0,0x0 > > l.addi r27,r0,0x0 > > l.addi
> > r28,r0,0x0 > > l.addi r29,r0,0x0 > > l.addi r30,r0,0x0
> > > > l.addi r31,r0,0x0 > > > > l.movhi
> > r3,hi(SDRAM_BASE_ADDR) > > l.ori r3,r3,lo(SDRAM_BASE_ADDR)
> > > > l.addi r5,r0,0x00 > > l.sw 0(r3),r5 > >
> > l.movhi r3,hi(_start) > > l.ori r3,r3,lo(_start) > >
> > l.jr r3 > > l.nop > > .section .text > > >
> > > _start: > > l.movhi r1,hi(_stack-4) > > l.ori
> > r1,r1,lo(_stack-4) > > l.addi r2,r0,-3 > > l.and
> > r1,r1,r2 > > > > l.movhi r2,hi(_main) > > l.ori
> > r2,r2,lo(_main) > > l.jr r2 > > l.nop > > >
> > > ___main: > > l.jr r9 > > l.nop > > >
> > > Then I use the following step to generate hex file: > >
> > or32-uclinux-gcc -g -c -o reset.o reset.S > > or32-uclinux-ld
> > -Tram.ld -o hello.or32 reset.o hello.o > >
> > or32-uclinux-objcopy -O binary hello.or32 hello.bin > >
> > or32-uclinux-objcopy -S -O ihex hello.or32 hello.hex > > >
> > > > > ----- Original Message ----- > > From: Robert
> > Cragie<rcc at j...> > > To: > > Date: Mon Nov 19
> > 09:24:52 CET 2007 > > Subject: [openrisc] how to run hello
> > world in on-chip ram? > > > > > 1) The CPU always
> > vectors to 0x100 on reset so you will either need > > >
> > some > > > sort of bootstrap there or you will have to map
> > RAM which you can > > > download > > > to there.
> > > > > 2) You can always get to intelhex from the ELF file
> > using: > > > or32-uclinux-objcopy -S -O ihex
> > <ELFfile> <ihexfile> > > > Robert Cragie,
> > Design Engineer > > > > >
> >
> _____________________________________________________________
>  >
> > > __ > > > Jennic Ltd, Furnival Street, Sheffield, S1
> > 4QT, UK > > > http://www.jennic.com Tel: [phone]
> > 2655 > > > > >
> >
> _____________________________________________________________
>  >
> > > __ > > > > -----Original Message----- > >
> > > > From: openrisc-bounces at opencores.org > > >
> > > [mailto:openrisc-bounces at opencores.org]On Behalf Of charlie
> > > > > yang > > > > Sent: 19 November 2007
> > 04:17 > > > > To: openrisc at opencores.org > >
> > > > Subject: [openrisc] how to run hello world in on-chip
> > ram? > > > > > > > > > > > > hi
> > all, > > > > I have a altera FPGA board with Cyclone II
> > EP2c35 and > > > synthesize the > > > >
> > orp_soc following the hardware tutorials. I have only one > >
> > > dedicated > > > > JTAG for FPGA and have no pins
> > for or1k CPU. So I want to burn > > > > the "hello
> > world" program into on-chip ram by > > > initializing
> > this memory, > > > > that is, let the JTAG download the
> > all the CPU and program . > > > > so there are two
> > questions for help: > > > > 1) how to set start pointer
> > of the reset.S and let the > > > "hello > >
> > > > world" run. > > > > 2) I find the
> > hello.hex in or1k is incompatible with Intel hex > > >
> > > format of > > > > altera memory. how can I convert
> > it to altera memory format? > > > > > > > >
> > Is there anybody using altera FPGA? Please give me some > >
> > > directions . > > > > Thanks a lot ! > > >
> > > _______________________________________________ > > >
> > > http://www.opencores.org/mailman/listinfo/openrisc > >
> > > > > >
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc

_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[charlie yang]

Thanks Robert.
I find where is the problem ,but dont' know why.
When I use or32-uclinux-objcopy command to get the ram.hex,
the "_start" physical address in RAM is 0x100, and CPU cannot jump
there.
But if i use orp_soc/sw/utils/bin2hex to convert the hello.bin to hello.hex
(it's not the intel hex format),then copy the content of hello.hex to
altera ram.hex, my hello-uart runs ok. But in this condition the physical
address of "_start" is 0x40 (right shift 2 bit than 0x100). These two
kinds of hex files come from the same hello.bin or hello.or32, why make
out the different start address?


The following is the file using "or32-uclinux-dump -d hello.or32":


hello.or32:     file format elf32-or32

Disassembly of section .vectors:

00000000 <_start-0x100>:
        ...

00000100 <_start>:
 100: 18 20 00 00 l.movhi r1,0x0
 104: a8 21 0d 52 l.ori r1,r1,0xd52
 108: 9c 40 ff fd l.addi r2,r0,0xfffffffd
 10c: e0 21 10 03 l.and r1,r1,r2
 110: 18 40 00 00 l.movhi r2,0x0
 114: a8 42 06 50 l.ori r2,r2,0x650
 118: 44 00 10 00 l.jr r2
 11c: 9c 40 00 00 l.addi r2,r0,0x0

00000120 <___main>:
 120: 44 00 48 00 l.jr r9
 124: 15 00 00 00 l.nop 0x0
Disassembly of section .text:

00000200 <_uart_init>:
 200: 9c 21 ff 44 l.addi r1,r1,0xffffff44
 204: d4 01 10 00 l.sw 0x0(r1),r2
 208: 9c 41 00 bc l.addi r2,r1,0xbc
 20c: 18 60 90 00 l.movhi r3,0x9000
 210: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
 214: 84 82 ff f4 l.lwz r4,0xfffffff4(r2)
 218: a8 84 00 02 l.ori r4,r4,0x2
 21c: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4
 220: 9c 60 ff c7 l.addi r3,r0,0xffffffc7
 224: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
 228: 84 82 ff f0 l.lwz r4,0xfffffff0(r2)
 22c: db e2 27 ef l.sb 0xffffffef(r2),r4
 230: 8c 82 ff ef l.lbz r4,0xffffffef(r2)
 234: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
 238: d8 03 20 00 l.sb 0x0(r3),r4
 23c: 18 60 90 00 l.movhi r3,0x9000
 240: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
 244: 84 82 ff e4 l.lwz r4,0xffffffe4(r2)
 248: a8 84 00 01 l.ori r4,r4,0x1
 24c: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4
 250: 9c 60 00 00 l.addi r3,r0,0x0
 254: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
 258: 84 82 ff e0 l.lwz r4,0xffffffe0(r2)
 25c: db e2 27 df l.sb 0xffffffdf(r2),r4
 260: 8c 82 ff df l.lbz r4,0xffffffdf(r2)
 264: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
 268: d8 03 20 00 l.sb 0x0(r3),r4
 26c: 18 60 90 00 l.movhi r3,0x9000
 270: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
 274: 84 82 ff d4 l.lwz r4,0xffffffd4(r2)
 278: a8 84 00 03 l.ori r4,r4,0x3
 27c: d7 e2 27 d8 l.sw 0xffffffd8(r2),r4
 280: 9c 60 00 03 l.addi r3,r0,0x3
 284: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
 288: 84 82 ff d0 l.lwz r4,0xffffffd0(r2)
 28c: db e2 27 cf l.sb 0xffffffcf(r2),r4
 290: 8c 82 ff cf l.lbz r4,0xffffffcf(r2)
 294: 84 62 ff d8 l.lwz r3,0xffffffd8(r2)
 298: d8 03 20 00 l.sb 0x0(r3),r4
 29c: 9c 60 00 41 l.addi r3,r0,0x41
 2a0: d7 e2 1f c8 l.sw 0xffffffc8(r2),r3
 2a4: 84 82 ff c8 l.lwz r4,0xffffffc8(r2)
 2a8: d7 e2 27 fc l.sw 0xfffffffc(r2),r4
 2ac: 18 60 90 00 l.movhi r3,0x9000
 2b0: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3
 2b4: 84 82 ff c0 l.lwz r4,0xffffffc0(r2)
 2b8: a8 84 00 03 l.ori r4,r4,0x3
 2bc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4
 2c0: 18 60 90 00 l.movhi r3,0x9000
 2c4: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3
 2c8: 84 82 ff b8 l.lwz r4,0xffffffb8(r2)
 2cc: a8 84 00 03 l.ori r4,r4,0x3
 2d0: d7 e2 27 bc l.sw 0xffffffbc(r2),r4
 2d4: 84 62 ff bc l.lwz r3,0xffffffbc(r2)
 2d8: 8c 63 00 00 l.lbz r3,0x0(r3)
 2dc: db e2 1f b7 l.sb 0xffffffb7(r2),r3
 2e0: 9c 60 ff 80 l.addi r3,r0,0xffffff80
 2e4: 8c 82 ff b7 l.lbz r4,0xffffffb7(r2)
 2e8: e0 64 18 04 l.or r3,r4,r3
 2ec: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3
 2f0: 84 82 ff b0 l.lwz r4,0xffffffb0(r2)
 2f4: db e2 27 af l.sb 0xffffffaf(r2),r4
 2f8: 8c 82 ff af l.lbz r4,0xffffffaf(r2)
 2fc: 84 62 ff c4 l.lwz r3,0xffffffc4(r2)
 300: d8 03 20 00 l.sb 0x0(r3),r4
 304: 18 60 90 00 l.movhi r3,0x9000
 308: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3
 30c: 84 82 ff fc l.lwz r4,0xfffffffc(r2)
 310: d7 e2 27 a4 l.sw 0xffffffa4(r2),r4
 314: 9c 60 ff ff l.addi r3,r0,0xffffffff
 318: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3
 31c: 84 82 ff 9c l.lwz r4,0xffffff9c(r2)
 320: db e2 27 a3 l.sb 0xffffffa3(r2),r4
 324: 84 62 ff a4 l.lwz r3,0xffffffa4(r2)
 328: db e2 1f 9b l.sb 0xffffff9b(r2),r3
 32c: 8c 82 ff 9b l.lbz r4,0xffffff9b(r2)
 330: 8c 62 ff a3 l.lbz r3,0xffffffa3(r2)
 334: e0 84 18 03 l.and r4,r4,r3
 338: d7 e2 27 94 l.sw 0xffffff94(r2),r4
 33c: 84 82 ff 94 l.lwz r4,0xffffff94(r2)
 340: db e2 27 93 l.sb 0xffffff93(r2),r4
 344: 8c 82 ff 93 l.lbz r4,0xffffff93(r2)
 348: 84 62 ff a8 l.lwz r3,0xffffffa8(r2)
 34c: d8 03 20 00 l.sb 0x0(r3),r4
 350: 18 60 90 00 l.movhi r3,0x9000
 354: d7 e2 1f 88 l.sw 0xffffff88(r2),r3
 358: 84 82 ff 88 l.lwz r4,0xffffff88(r2)
 35c: a8 84 00 01 l.ori r4,r4,0x1
 360: d7 e2 27 8c l.sw 0xffffff8c(r2),r4
 364: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
 368: d7 e2 1f 80 l.sw 0xffffff80(r2),r3
 36c: 84 82 ff 80 l.lwz r4,0xffffff80(r2)
 370: b8 84 00 88 l.srai r4,r4,0x8
 374: d7 e2 27 84 l.sw 0xffffff84(r2),r4
 378: 9c 60 ff ff l.addi r3,r0,0xffffffff
 37c: d7 e2 1f 78 l.sw 0xffffff78(r2),r3
 380: 84 82 ff 78 l.lwz r4,0xffffff78(r2)
 384: db e2 27 7f l.sb 0xffffff7f(r2),r4
 388: 84 62 ff 84 l.lwz r3,0xffffff84(r2)
 38c: db e2 1f 77 l.sb 0xffffff77(r2),r3
 390: 8c 82 ff 77 l.lbz r4,0xffffff77(r2)
 394: 8c 62 ff 7f l.lbz r3,0xffffff7f(r2)
 398: e0 84 18 03 l.and r4,r4,r3
 39c: d7 e2 27 70 l.sw 0xffffff70(r2),r4
 3a0: 84 82 ff 70 l.lwz r4,0xffffff70(r2)
 3a4: db e2 27 6f l.sb 0xffffff6f(r2),r4
 3a8: 8c 82 ff 6f l.lbz r4,0xffffff6f(r2)
 3ac: 84 62 ff 8c l.lwz r3,0xffffff8c(r2)
 3b0: d8 03 20 00 l.sb 0x0(r3),r4
 3b4: 18 60 90 00 l.movhi r3,0x9000
 3b8: d7 e2 1f 64 l.sw 0xffffff64(r2),r3
 3bc: 84 82 ff 64 l.lwz r4,0xffffff64(r2)
 3c0: a8 84 00 03 l.ori r4,r4,0x3
 3c4: d7 e2 27 68 l.sw 0xffffff68(r2),r4
 3c8: 18 60 90 00 l.movhi r3,0x9000
 3cc: d7 e2 1f 5c l.sw 0xffffff5c(r2),r3
 3d0: 84 82 ff 5c l.lwz r4,0xffffff5c(r2)
 3d4: a8 84 00 03 l.ori r4,r4,0x3
 3d8: d7 e2 27 60 l.sw 0xffffff60(r2),r4
 3dc: 9c 60 00 7f l.addi r3,r0,0x7f
 3e0: d7 e2 1f 54 l.sw 0xffffff54(r2),r3
 3e4: 84 82 ff 54 l.lwz r4,0xffffff54(r2)
 3e8: db e2 27 5b l.sb 0xffffff5b(r2),r4
 3ec: 84 62 ff 60 l.lwz r3,0xffffff60(r2)
 3f0: 8c 63 00 00 l.lbz r3,0x0(r3)
 3f4: db e2 1f 53 l.sb 0xffffff53(r2),r3
 3f8: 8c 82 ff 53 l.lbz r4,0xffffff53(r2)
 3fc: 8c 62 ff 5b l.lbz r3,0xffffff5b(r2)
 400: e0 84 18 03 l.and r4,r4,r3
 404: d7 e2 27 4c l.sw 0xffffff4c(r2),r4
 408: 84 82 ff 4c l.lwz r4,0xffffff4c(r2)
 40c: db e2 27 4b l.sb 0xffffff4b(r2),r4
 410: 8c 82 ff 4b l.lbz r4,0xffffff4b(r2)
 414: 84 62 ff 68 l.lwz r3,0xffffff68(r2)
 418: d8 03 20 00 l.sb 0x0(r3),r4
 41c: 84 41 00 00 l.lwz r2,0x0(r1)
 420: 44 00 48 00 l.jr r9
 424: 9c 21 00 bc l.addi r1,r1,0xbc

00000428 <_uart_putc>:
 428: 9c 21 ff 9c l.addi r1,r1,0xffffff9c
 42c: d4 01 10 00 l.sw 0x0(r1),r2
 430: 9c 41 00 64 l.addi r2,r1,0x64
 434: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3
 438: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
 43c: db e2 1f f7 l.sb 0xfffffff7(r2),r3
 440: 8c 82 ff f7 l.lbz r4,0xfffffff7(r2)
 444: db e2 27 ff l.sb 0xffffffff(r2),r4
 448: 18 60 90 00 l.movhi r3,0x9000
 44c: d7 e2 1f ec l.sw 0xffffffec(r2),r3
 450: 84 82 ff ec l.lwz r4,0xffffffec(r2)
 454: a8 84 00 05 l.ori r4,r4,0x5
 458: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4
 45c: 84 62 ff f0 l.lwz r3,0xfffffff0(r2)
 460: 8c 63 00 00 l.lbz r3,0x0(r3)
 464: db e2 1f eb l.sb 0xffffffeb(r2),r3
 468: 8c 82 ff eb l.lbz r4,0xffffffeb(r2)
 46c: db e2 27 fe l.sb 0xfffffffe(r2),r4
 470: 8c 62 ff fe l.lbz r3,0xfffffffe(r2)
 474: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
 478: 84 82 ff e4 l.lwz r4,0xffffffe4(r2)
 47c: a4 84 00 20 l.andi r4,r4,0x20
 480: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4
 484: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
 488: bc 23 00 00 l.sfnei r3,0x0
 48c: 10 00 00 04 l.bf 49c <_uart_putc+0x74>
 490: 15 00 00 00 l.nop 0x0
 494: 03 ff ff ed l.j 448 <_uart_putc+0x20>
 498: 15 00 00 00 l.nop 0x0
 49c: 18 80 90 00 l.movhi r4,0x9000
 4a0: d7 e2 27 dc l.sw 0xffffffdc(r2),r4
 4a4: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
 4a8: db e2 1f db l.sb 0xffffffdb(r2),r3
 4ac: 8c 62 ff db l.lbz r3,0xffffffdb(r2)
 4b0: 84 82 ff dc l.lwz r4,0xffffffdc(r2)
 4b4: d8 04 18 00 l.sb 0x0(r4),r3
 4b8: 90 82 ff ff l.lbs r4,0xffffffff(r2)
 4bc: d7 e2 27 d4 l.sw 0xffffffd4(r2),r4
 4c0: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
 4c4: bc 23 00 0a l.sfnei r3,0xa
 4c8: 10 00 00 20 l.bf 548 <_uart_putc+0x120>
 4cc: 15 00 00 00 l.nop 0x0
 4d0: 18 80 90 00 l.movhi r4,0x9000
 4d4: d7 e2 27 cc l.sw 0xffffffcc(r2),r4
 4d8: 84 62 ff cc l.lwz r3,0xffffffcc(r2)
 4dc: a8 63 00 05 l.ori r3,r3,0x5
 4e0: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
 4e4: 84 82 ff d0 l.lwz r4,0xffffffd0(r2)
 4e8: 8c 84 00 00 l.lbz r4,0x0(r4)
 4ec: db e2 27 cb l.sb 0xffffffcb(r2),r4
 4f0: 8c 62 ff cb l.lbz r3,0xffffffcb(r2)
 4f4: db e2 1f fe l.sb 0xfffffffe(r2),r3
 4f8: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
 4fc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4
 500: 84 62 ff c4 l.lwz r3,0xffffffc4(r2)
 504: a4 63 00 20 l.andi r3,r3,0x20
 508: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3
 50c: 84 82 ff c0 l.lwz r4,0xffffffc0(r2)
 510: bc 24 00 00 l.sfnei r4,0x0
 514: 10 00 00 04 l.bf 524 <_uart_putc+0xfc>
 518: 15 00 00 00 l.nop 0x0
 51c: 03 ff ff ed l.j 4d0 <_uart_putc+0xa8>
 520: 15 00 00 00 l.nop 0x0
 524: 18 60 90 00 l.movhi r3,0x9000
 528: d7 e2 1f bc l.sw 0xffffffbc(r2),r3
 52c: 9c 80 00 0d l.addi r4,r0,0xd
 530: d7 e2 27 b8 l.sw 0xffffffb8(r2),r4
 534: 84 62 ff b8 l.lwz r3,0xffffffb8(r2)
 538: db e2 1f b7 l.sb 0xffffffb7(r2),r3
 53c: 8c 62 ff b7 l.lbz r3,0xffffffb7(r2)
 540: 84 82 ff bc l.lwz r4,0xffffffbc(r2)
 544: d8 04 18 00 l.sb 0x0(r4),r3
 548: 18 80 90 00 l.movhi r4,0x9000
 54c: d7 e2 27 ac l.sw 0xffffffac(r2),r4
 550: 84 62 ff ac l.lwz r3,0xffffffac(r2)
 554: a8 63 00 05 l.ori r3,r3,0x5
 558: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3
 55c: 84 82 ff b0 l.lwz r4,0xffffffb0(r2)
 560: 8c 84 00 00 l.lbz r4,0x0(r4)
 564: db e2 27 ab l.sb 0xffffffab(r2),r4
 568: 8c 62 ff ab l.lbz r3,0xffffffab(r2)
 56c: db e2 1f fe l.sb 0xfffffffe(r2),r3
 570: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
 574: d7 e2 27 a4 l.sw 0xffffffa4(r2),r4
 578: 84 62 ff a4 l.lwz r3,0xffffffa4(r2)
 57c: a4 63 00 60 l.andi r3,r3,0x60
 580: d7 e2 1f a0 l.sw 0xffffffa0(r2),r3
 584: 84 82 ff a0 l.lwz r4,0xffffffa0(r2)
 588: bc 04 00 60 l.sfeqi r4,0x60
 58c: 10 00 00 04 l.bf 59c <_uart_putc+0x174>
 590: 15 00 00 00 l.nop 0x0
 594: 03 ff ff ed l.j 548 <_uart_putc+0x120>
 598: 15 00 00 00 l.nop 0x0
 59c: 84 41 00 00 l.lwz r2,0x0(r1)
 5a0: 44 00 48 00 l.jr r9
 5a4: 9c 21 00 64 l.addi r1,r1,0x64

000005a8 <_uart_getc>:
 5a8: 9c 21 ff d0 l.addi r1,r1,0xffffffd0
 5ac: d4 01 10 00 l.sw 0x0(r1),r2
 5b0: 9c 41 00 30 l.addi r2,r1,0x30
 5b4: 18 60 90 00 l.movhi r3,0x9000
 5b8: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
 5bc: 84 62 ff f0 l.lwz r3,0xfffffff0(r2)
 5c0: a8 63 00 05 l.ori r3,r3,0x5
 5c4: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
 5c8: 84 62 ff f4 l.lwz r3,0xfffffff4(r2)
 5cc: 8c 63 00 00 l.lbz r3,0x0(r3)
 5d0: db e2 1f ef l.sb 0xffffffef(r2),r3
 5d4: 8c 62 ff ef l.lbz r3,0xffffffef(r2)
 5d8: db e2 1f ff l.sb 0xffffffff(r2),r3
 5dc: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
 5e0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3
 5e4: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
 5e8: ac 63 00 01 l.xori r3,r3,0x1
 5ec: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
 5f0: 84 62 ff e4 l.lwz r3,0xffffffe4(r2)
 5f4: a4 63 00 01 l.andi r3,r3,0x1
 5f8: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
 5fc: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
 600: bc 03 00 00 l.sfeqi r3,0x0
 604: 10 00 00 04 l.bf 614 <_uart_getc+0x6c>
 608: 15 00 00 00 l.nop 0x0
 60c: 03 ff ff ea l.j 5b4 <_uart_getc+0xc>
 610: 15 00 00 00 l.nop 0x0
 614: 18 60 90 00 l.movhi r3,0x9000
 618: d7 e2 1f dc l.sw 0xffffffdc(r2),r3
 61c: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
 620: 8c 63 00 00 l.lbz r3,0x0(r3)
 624: db e2 1f db l.sb 0xffffffdb(r2),r3
 628: 8c 62 ff db l.lbz r3,0xffffffdb(r2)
 62c: db e2 1f fe l.sb 0xfffffffe(r2),r3
 630: 90 62 ff fe l.lbs r3,0xfffffffe(r2)
 634: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
 638: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
 63c: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3
 640: 85 62 ff f8 l.lwz r11,0xfffffff8(r2)
 644: 84 41 00 00 l.lwz r2,0x0(r1)
 648: 44 00 48 00 l.jr r9
 64c: 9c 21 00 30 l.addi r1,r1,0x30

00000650 <_main>:
 650: 9c 21 ff c4 l.addi r1,r1,0xffffffc4
 654: d4 01 10 04 l.sw 0x4(r1),r2
 658: 9c 41 00 3c l.addi r2,r1,0x3c
 65c: d4 01 48 00 l.sw 0x0(r1),r9
 660: 07 ff fe e8 l.jal 200 <_uart_init>
 664: 15 00 00 00 l.nop 0x0
 668: 18 60 00 00 l.movhi r3,0x0
 66c: a8 63 07 44 l.ori r3,r3,0x744
 670: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3
 674: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
 678: 84 63 00 00 l.lwz r3,0x0(r3)
 67c: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
 680: 84 62 ff f4 l.lwz r3,0xfffffff4(r2)
 684: d7 e2 1f fc l.sw 0xfffffffc(r2),r3
 688: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
 68c: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
 690: 84 62 ff f0 l.lwz r3,0xfffffff0(r2)
 694: 90 63 00 00 l.lbs r3,0x0(r3)
 698: d7 e2 1f ec l.sw 0xffffffec(r2),r3
 69c: 84 62 ff ec l.lwz r3,0xffffffec(r2)
 6a0: bc 03 00 00 l.sfeqi r3,0x0
 6a4: 10 00 00 13 l.bf 6f0 <_main+0xa0>
 6a8: 15 00 00 00 l.nop 0x0
 6ac: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
 6b0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3
 6b4: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
 6b8: 90 63 00 00 l.lbs r3,0x0(r3)
 6bc: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
 6c0: 84 62 ff e4 l.lwz r3,0xffffffe4(r2)
 6c4: 07 ff ff 59 l.jal 428 <_uart_putc>
 6c8: 15 00 00 00 l.nop 0x0
 6cc: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
 6d0: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
 6d4: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
 6d8: 9c 63 00 01 l.addi r3,r3,0x1
 6dc: d7 e2 1f dc l.sw 0xffffffdc(r2),r3
 6e0: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
 6e4: d7 e2 1f fc l.sw 0xfffffffc(r2),r3
 6e8: 03 ff ff e8 l.j 688 <_main+0x38>
 6ec: 15 00 00 00 l.nop 0x0
 6f0: 07 ff ff ae l.jal 5a8 <_uart_getc>
 6f4: 15 00 00 00 l.nop 0x0
 6f8: d7 e2 5f d8 l.sw 0xffffffd8(r2),r11
 6fc: 84 62 ff d8 l.lwz r3,0xffffffd8(r2)
 700: 9c 63 00 01 l.addi r3,r3,0x1
 704: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
 708: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
 70c: b8 63 00 18 l.slli r3,r3,0x18
 710: d7 e2 1f cc l.sw 0xffffffcc(r2),r3
 714: 84 62 ff cc l.lwz r3,0xffffffcc(r2)
 718: b8 63 00 98 l.srai r3,r3,0x18
 71c: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
 720: 84 62 ff d0 l.lwz r3,0xffffffd0(r2)
 724: 07 ff ff 41 l.jal 428 <_uart_putc>
 728: 15 00 00 00 l.nop 0x0
 72c: 03 ff ff f1 l.j 6f0 <_main+0xa0>
 730: 15 00 00 00 l.nop 0x0
 734: 85 21 00 00 l.lwz r9,0x0(r1)
 738: 84 41 00 04 l.lwz r2,0x4(r1)
 73c: 44 00 48 00 l.jr r9
 740: 9c 21 00 3c l.addi r1,r1,0x3c



----- Original Message -----
From: Robert Cragie<rcc@j...>
To:
Date: Thu Nov 22 11:30:49 CET 2007
Subject: [openrisc] how to run hello world in on-chip ram?

> Can you post the disassembly of your hello.or32 file?:
>
> or32-uclinux-objdump -d hello.or32
>
> That will give a clearer picture of where everything is.
>
> Robert
>
> Robert Cragie, Design Engineer
>

_____________________________________________________________
__
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> http://www.jennic.com Tel: [phone]
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[Robert Cragie]

OK, I guess the Intelhex bit ended up being misleading. I have never
actually attempted what you are doing. With respect to the addresses, again
I guess that the address bus to the memory actually starts at address bit 2,
with address bits 1 and 0 decoded for the byte lanes of 32-bit wide memory.
Therefore it seems reasonable to me that the address *lines* will appear to
be shifted by 2 as you state.

Robert

Robert Cragie, Design Engineer
_______________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
http://www.jennic.com  Tel: [phone]
_______________________________________________________________

> -----Original Message-----
> From: openrisc-bounces@...
> [mailto:openrisc-bounces@...]On Behalf Of charlie yang
> Sent: 23 November 2007 01:58
> To: openrisc@...
> Subject: Re: [openrisc] how to run hello world in on-chip ram?
>
>
> Thanks Robert.
> I find where is the problem ,but dont' know why.
> When I use or32-uclinux-objcopy command to get the ram.hex,
> the "_start" physical address in RAM is 0x100, and CPU cannot jump
> there.
> But if i use orp_soc/sw/utils/bin2hex to convert the hello.bin to
> hello.hex
> (it's not the intel hex format),then copy the content of hello.hex to
> altera ram.hex, my hello-uart runs ok. But in this condition the physical
> address of "_start" is 0x40 (right shift 2 bit than 0x100). These two
> kinds of hex files come from the same hello.bin or hello.or32, why make
> out the different start address?
>
>
> The following is the file using "or32-uclinux-dump -d hello.or32":
>
>
> hello.or32:     file format elf32-or32
>
> Disassembly of section .vectors:
>
> 00000000 <_start-0x100>:
> ...
>
> 00000100 <_start>:
>  100: 18 20 00 00 l.movhi r1,0x0
>  104: a8 21 0d 52 l.ori r1,r1,0xd52
>  108: 9c 40 ff fd l.addi r2,r0,0xfffffffd
>  10c: e0 21 10 03 l.and r1,r1,r2
>  110: 18 40 00 00 l.movhi r2,0x0
>  114: a8 42 06 50 l.ori r2,r2,0x650
>  118: 44 00 10 00 l.jr r2
>  11c: 9c 40 00 00 l.addi r2,r0,0x0
>
> 00000120 <___main>:
>  120: 44 00 48 00 l.jr r9
>  124: 15 00 00 00 l.nop 0x0
> Disassembly of section .text:
>
> 00000200 <_uart_init>:
>  200: 9c 21 ff 44 l.addi r1,r1,0xffffff44
>  204: d4 01 10 00 l.sw 0x0(r1),r2
>  208: 9c 41 00 bc l.addi r2,r1,0xbc
>  20c: 18 60 90 00 l.movhi r3,0x9000
>  210: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
>  214: 84 82 ff f4 l.lwz r4,0xfffffff4(r2)
>  218: a8 84 00 02 l.ori r4,r4,0x2
>  21c: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4
>  220: 9c 60 ff c7 l.addi r3,r0,0xffffffc7
>  224: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
>  228: 84 82 ff f0 l.lwz r4,0xfffffff0(r2)
>  22c: db e2 27 ef l.sb 0xffffffef(r2),r4
>  230: 8c 82 ff ef l.lbz r4,0xffffffef(r2)
>  234: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
>  238: d8 03 20 00 l.sb 0x0(r3),r4
>  23c: 18 60 90 00 l.movhi r3,0x9000
>  240: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
>  244: 84 82 ff e4 l.lwz r4,0xffffffe4(r2)
>  248: a8 84 00 01 l.ori r4,r4,0x1
>  24c: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4
>  250: 9c 60 00 00 l.addi r3,r0,0x0
>  254: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
>  258: 84 82 ff e0 l.lwz r4,0xffffffe0(r2)
>  25c: db e2 27 df l.sb 0xffffffdf(r2),r4
>  260: 8c 82 ff df l.lbz r4,0xffffffdf(r2)
>  264: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
>  268: d8 03 20 00 l.sb 0x0(r3),r4
>  26c: 18 60 90 00 l.movhi r3,0x9000
>  270: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
>  274: 84 82 ff d4 l.lwz r4,0xffffffd4(r2)
>  278: a8 84 00 03 l.ori r4,r4,0x3
>  27c: d7 e2 27 d8 l.sw 0xffffffd8(r2),r4
>  280: 9c 60 00 03 l.addi r3,r0,0x3
>  284: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
>  288: 84 82 ff d0 l.lwz r4,0xffffffd0(r2)
>  28c: db e2 27 cf l.sb 0xffffffcf(r2),r4
>  290: 8c 82 ff cf l.lbz r4,0xffffffcf(r2)
>  294: 84 62 ff d8 l.lwz r3,0xffffffd8(r2)
>  298: d8 03 20 00 l.sb 0x0(r3),r4
>  29c: 9c 60 00 41 l.addi r3,r0,0x41
>  2a0: d7 e2 1f c8 l.sw 0xffffffc8(r2),r3
>  2a4: 84 82 ff c8 l.lwz r4,0xffffffc8(r2)
>  2a8: d7 e2 27 fc l.sw 0xfffffffc(r2),r4
>  2ac: 18 60 90 00 l.movhi r3,0x9000
>  2b0: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3
>  2b4: 84 82 ff c0 l.lwz r4,0xffffffc0(r2)
>  2b8: a8 84 00 03 l.ori r4,r4,0x3
>  2bc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4
>  2c0: 18 60 90 00 l.movhi r3,0x9000
>  2c4: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3
>  2c8: 84 82 ff b8 l.lwz r4,0xffffffb8(r2)
>  2cc: a8 84 00 03 l.ori r4,r4,0x3
>  2d0: d7 e2 27 bc l.sw 0xffffffbc(r2),r4
>  2d4: 84 62 ff bc l.lwz r3,0xffffffbc(r2)
>  2d8: 8c 63 00 00 l.lbz r3,0x0(r3)
>  2dc: db e2 1f b7 l.sb 0xffffffb7(r2),r3
>  2e0: 9c 60 ff 80 l.addi r3,r0,0xffffff80
>  2e4: 8c 82 ff b7 l.lbz r4,0xffffffb7(r2)
>  2e8: e0 64 18 04 l.or r3,r4,r3
>  2ec: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3
>  2f0: 84 82 ff b0 l.lwz r4,0xffffffb0(r2)
>  2f4: db e2 27 af l.sb 0xffffffaf(r2),r4
>  2f8: 8c 82 ff af l.lbz r4,0xffffffaf(r2)
>  2fc: 84 62 ff c4 l.lwz r3,0xffffffc4(r2)
>  300: d8 03 20 00 l.sb 0x0(r3),r4
>  304: 18 60 90 00 l.movhi r3,0x9000
>  308: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3
>  30c: 84 82 ff fc l.lwz r4,0xfffffffc(r2)
>  310: d7 e2 27 a4 l.sw 0xffffffa4(r2),r4
>  314: 9c 60 ff ff l.addi r3,r0,0xffffffff
>  318: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3
>  31c: 84 82 ff 9c l.lwz r4,0xffffff9c(r2)
>  320: db e2 27 a3 l.sb 0xffffffa3(r2),r4
>  324: 84 62 ff a4 l.lwz r3,0xffffffa4(r2)
>  328: db e2 1f 9b l.sb 0xffffff9b(r2),r3
>  32c: 8c 82 ff 9b l.lbz r4,0xffffff9b(r2)
>  330: 8c 62 ff a3 l.lbz r3,0xffffffa3(r2)
>  334: e0 84 18 03 l.and r4,r4,r3
>  338: d7 e2 27 94 l.sw 0xffffff94(r2),r4
>  33c: 84 82 ff 94 l.lwz r4,0xffffff94(r2)
>  340: db e2 27 93 l.sb 0xffffff93(r2),r4
>  344: 8c 82 ff 93 l.lbz r4,0xffffff93(r2)
>  348: 84 62 ff a8 l.lwz r3,0xffffffa8(r2)
>  34c: d8 03 20 00 l.sb 0x0(r3),r4
>  350: 18 60 90 00 l.movhi r3,0x9000
>  354: d7 e2 1f 88 l.sw 0xffffff88(r2),r3
>  358: 84 82 ff 88 l.lwz r4,0xffffff88(r2)
>  35c: a8 84 00 01 l.ori r4,r4,0x1
>  360: d7 e2 27 8c l.sw 0xffffff8c(r2),r4
>  364: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
>  368: d7 e2 1f 80 l.sw 0xffffff80(r2),r3
>  36c: 84 82 ff 80 l.lwz r4,0xffffff80(r2)
>  370: b8 84 00 88 l.srai r4,r4,0x8
>  374: d7 e2 27 84 l.sw 0xffffff84(r2),r4
>  378: 9c 60 ff ff l.addi r3,r0,0xffffffff
>  37c: d7 e2 1f 78 l.sw 0xffffff78(r2),r3
>  380: 84 82 ff 78 l.lwz r4,0xffffff78(r2)
>  384: db e2 27 7f l.sb 0xffffff7f(r2),r4
>  388: 84 62 ff 84 l.lwz r3,0xffffff84(r2)
>  38c: db e2 1f 77 l.sb 0xffffff77(r2),r3
>  390: 8c 82 ff 77 l.lbz r4,0xffffff77(r2)
>  394: 8c 62 ff 7f l.lbz r3,0xffffff7f(r2)
>  398: e0 84 18 03 l.and r4,r4,r3
>  39c: d7 e2 27 70 l.sw 0xffffff70(r2),r4
>  3a0: 84 82 ff 70 l.lwz r4,0xffffff70(r2)
>  3a4: db e2 27 6f l.sb 0xffffff6f(r2),r4
>  3a8: 8c 82 ff 6f l.lbz r4,0xffffff6f(r2)
>  3ac: 84 62 ff 8c l.lwz r3,0xffffff8c(r2)
>  3b0: d8 03 20 00 l.sb 0x0(r3),r4
>  3b4: 18 60 90 00 l.movhi r3,0x9000
>  3b8: d7 e2 1f 64 l.sw 0xffffff64(r2),r3
>  3bc: 84 82 ff 64 l.lwz r4,0xffffff64(r2)
>  3c0: a8 84 00 03 l.ori r4,r4,0x3
>  3c4: d7 e2 27 68 l.sw 0xffffff68(r2),r4
>  3c8: 18 60 90 00 l.movhi r3,0x9000
>  3cc: d7 e2 1f 5c l.sw 0xffffff5c(r2),r3
>  3d0: 84 82 ff 5c l.lwz r4,0xffffff5c(r2)
>  3d4: a8 84 00 03 l.ori r4,r4,0x3
>  3d8: d7 e2 27 60 l.sw 0xffffff60(r2),r4
>  3dc: 9c 60 00 7f l.addi r3,r0,0x7f
>  3e0: d7 e2 1f 54 l.sw 0xffffff54(r2),r3
>  3e4: 84 82 ff 54 l.lwz r4,0xffffff54(r2)
>  3e8: db e2 27 5b l.sb 0xffffff5b(r2),r4
>  3ec: 84 62 ff 60 l.lwz r3,0xffffff60(r2)
>  3f0: 8c 63 00 00 l.lbz r3,0x0(r3)
>  3f4: db e2 1f 53 l.sb 0xffffff53(r2),r3
>  3f8: 8c 82 ff 53 l.lbz r4,0xffffff53(r2)
>  3fc: 8c 62 ff 5b l.lbz r3,0xffffff5b(r2)
>  400: e0 84 18 03 l.and r4,r4,r3
>  404: d7 e2 27 4c l.sw 0xffffff4c(r2),r4
>  408: 84 82 ff 4c l.lwz r4,0xffffff4c(r2)
>  40c: db e2 27 4b l.sb 0xffffff4b(r2),r4
>  410: 8c 82 ff 4b l.lbz r4,0xffffff4b(r2)
>  414: 84 62 ff 68 l.lwz r3,0xffffff68(r2)
>  418: d8 03 20 00 l.sb 0x0(r3),r4
>  41c: 84 41 00 00 l.lwz r2,0x0(r1)
>  420: 44 00 48 00 l.jr r9
>  424: 9c 21 00 bc l.addi r1,r1,0xbc
>
> 00000428 <_uart_putc>:
>  428: 9c 21 ff 9c l.addi r1,r1,0xffffff9c
>  42c: d4 01 10 00 l.sw 0x0(r1),r2
>  430: 9c 41 00 64 l.addi r2,r1,0x64
>  434: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3
>  438: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
>  43c: db e2 1f f7 l.sb 0xfffffff7(r2),r3
>  440: 8c 82 ff f7 l.lbz r4,0xfffffff7(r2)
>  444: db e2 27 ff l.sb 0xffffffff(r2),r4
>  448: 18 60 90 00 l.movhi r3,0x9000
>  44c: d7 e2 1f ec l.sw 0xffffffec(r2),r3
>  450: 84 82 ff ec l.lwz r4,0xffffffec(r2)
>  454: a8 84 00 05 l.ori r4,r4,0x5
>  458: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4
>  45c: 84 62 ff f0 l.lwz r3,0xfffffff0(r2)
>  460: 8c 63 00 00 l.lbz r3,0x0(r3)
>  464: db e2 1f eb l.sb 0xffffffeb(r2),r3
>  468: 8c 82 ff eb l.lbz r4,0xffffffeb(r2)
>  46c: db e2 27 fe l.sb 0xfffffffe(r2),r4
>  470: 8c 62 ff fe l.lbz r3,0xfffffffe(r2)
>  474: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
>  478: 84 82 ff e4 l.lwz r4,0xffffffe4(r2)
>  47c: a4 84 00 20 l.andi r4,r4,0x20
>  480: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4
>  484: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
>  488: bc 23 00 00 l.sfnei r3,0x0
>  48c: 10 00 00 04 l.bf 49c <_uart_putc+0x74>
>  490: 15 00 00 00 l.nop 0x0
>  494: 03 ff ff ed l.j 448 <_uart_putc+0x20>
>  498: 15 00 00 00 l.nop 0x0
>  49c: 18 80 90 00 l.movhi r4,0x9000
>  4a0: d7 e2 27 dc l.sw 0xffffffdc(r2),r4
>  4a4: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
>  4a8: db e2 1f db l.sb 0xffffffdb(r2),r3
>  4ac: 8c 62 ff db l.lbz r3,0xffffffdb(r2)
>  4b0: 84 82 ff dc l.lwz r4,0xffffffdc(r2)
>  4b4: d8 04 18 00 l.sb 0x0(r4),r3
>  4b8: 90 82 ff ff l.lbs r4,0xffffffff(r2)
>  4bc: d7 e2 27 d4 l.sw 0xffffffd4(r2),r4
>  4c0: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
>  4c4: bc 23 00 0a l.sfnei r3,0xa
>  4c8: 10 00 00 20 l.bf 548 <_uart_putc+0x120>
>  4cc: 15 00 00 00 l.nop 0x0
>  4d0: 18 80 90 00 l.movhi r4,0x9000
>  4d4: d7 e2 27 cc l.sw 0xffffffcc(r2),r4
>  4d8: 84 62 ff cc l.lwz r3,0xffffffcc(r2)
>  4dc: a8 63 00 05 l.ori r3,r3,0x5
>  4e0: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
>  4e4: 84 82 ff d0 l.lwz r4,0xffffffd0(r2)
>  4e8: 8c 84 00 00 l.lbz r4,0x0(r4)
>  4ec: db e2 27 cb l.sb 0xffffffcb(r2),r4
>  4f0: 8c 62 ff cb l.lbz r3,0xffffffcb(r2)
>  4f4: db e2 1f fe l.sb 0xfffffffe(r2),r3
>  4f8: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
>  4fc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4
>  500: 84 62 ff c4 l.lwz r3,0xffffffc4(r2)
>  504: a4 63 00 20 l.andi r3,r3,0x20
>  508: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3
>  50c: 84 82 ff c0 l.lwz r4,0xffffffc0(r2)
>  510: bc 24 00 00 l.sfnei r4,0x0
>  514: 10 00 00 04 l.bf 524 <_uart_putc+0xfc>
>  518: 15 00 00 00 l.nop 0x0
>  51c: 03 ff ff ed l.j 4d0 <_uart_putc+0xa8>
>  520: 15 00 00 00 l.nop 0x0
>  524: 18 60 90 00 l.movhi r3,0x9000
>  528: d7 e2 1f bc l.sw 0xffffffbc(r2),r3
>  52c: 9c 80 00 0d l.addi r4,r0,0xd
>  530: d7 e2 27 b8 l.sw 0xffffffb8(r2),r4
>  534: 84 62 ff b8 l.lwz r3,0xffffffb8(r2)
>  538: db e2 1f b7 l.sb 0xffffffb7(r2),r3
>  53c: 8c 62 ff b7 l.lbz r3,0xffffffb7(r2)
>  540: 84 82 ff bc l.lwz r4,0xffffffbc(r2)
>  544: d8 04 18 00 l.sb 0x0(r4),r3
>  548: 18 80 90 00 l.movhi r4,0x9000
>  54c: d7 e2 27 ac l.sw 0xffffffac(r2),r4
>  550: 84 62 ff ac l.lwz r3,0xffffffac(r2)
>  554: a8 63 00 05 l.ori r3,r3,0x5
>  558: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3
>  55c: 84 82 ff b0 l.lwz r4,0xffffffb0(r2)
>  560: 8c 84 00 00 l.lbz r4,0x0(r4)
>  564: db e2 27 ab l.sb 0xffffffab(r2),r4
>  568: 8c 62 ff ab l.lbz r3,0xffffffab(r2)
>  56c: db e2 1f fe l.sb 0xfffffffe(r2),r3
>  570: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
>  574: d7 e2 27 a4 l.sw 0xffffffa4(r2),r4
>  578: 84 62 ff a4 l.lwz r3,0xffffffa4(r2)
>  57c: a4 63 00 60 l.andi r3,r3,0x60
>  580: d7 e2 1f a0 l.sw 0xffffffa0(r2),r3
>  584: 84 82 ff a0 l.lwz r4,0xffffffa0(r2)
>  588: bc 04 00 60 l.sfeqi r4,0x60
>  58c: 10 00 00 04 l.bf 59c <_uart_putc+0x174>
>  590: 15 00 00 00 l.nop 0x0
>  594: 03 ff ff ed l.j 548 <_uart_putc+0x120>
>  598: 15 00 00 00 l.nop 0x0
>  59c: 84 41 00 00 l.lwz r2,0x0(r1)
>  5a0: 44 00 48 00 l.jr r9
>  5a4: 9c 21 00 64 l.addi r1,r1,0x64
>
> 000005a8 <_uart_getc>:
>  5a8: 9c 21 ff d0 l.addi r1,r1,0xffffffd0
>  5ac: d4 01 10 00 l.sw 0x0(r1),r2
>  5b0: 9c 41 00 30 l.addi r2,r1,0x30
>  5b4: 18 60 90 00 l.movhi r3,0x9000
>  5b8: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
>  5bc: 84 62 ff f0 l.lwz r3,0xfffffff0(r2)
>  5c0: a8 63 00 05 l.ori r3,r3,0x5
>  5c4: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
>  5c8: 84 62 ff f4 l.lwz r3,0xfffffff4(r2)
>  5cc: 8c 63 00 00 l.lbz r3,0x0(r3)
>  5d0: db e2 1f ef l.sb 0xffffffef(r2),r3
>  5d4: 8c 62 ff ef l.lbz r3,0xffffffef(r2)
>  5d8: db e2 1f ff l.sb 0xffffffff(r2),r3
>  5dc: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
>  5e0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3
>  5e4: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
>  5e8: ac 63 00 01 l.xori r3,r3,0x1
>  5ec: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
>  5f0: 84 62 ff e4 l.lwz r3,0xffffffe4(r2)
>  5f4: a4 63 00 01 l.andi r3,r3,0x1
>  5f8: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
>  5fc: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
>  600: bc 03 00 00 l.sfeqi r3,0x0
>  604: 10 00 00 04 l.bf 614 <_uart_getc+0x6c>
>  608: 15 00 00 00 l.nop 0x0
>  60c: 03 ff ff ea l.j 5b4 <_uart_getc+0xc>
>  610: 15 00 00 00 l.nop 0x0
>  614: 18 60 90 00 l.movhi r3,0x9000
>  618: d7 e2 1f dc l.sw 0xffffffdc(r2),r3
>  61c: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
>  620: 8c 63 00 00 l.lbz r3,0x0(r3)
>  624: db e2 1f db l.sb 0xffffffdb(r2),r3
>  628: 8c 62 ff db l.lbz r3,0xffffffdb(r2)
>  62c: db e2 1f fe l.sb 0xfffffffe(r2),r3
>  630: 90 62 ff fe l.lbs r3,0xfffffffe(r2)
>  634: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
>  638: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
>  63c: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3
>  640: 85 62 ff f8 l.lwz r11,0xfffffff8(r2)
>  644: 84 41 00 00 l.lwz r2,0x0(r1)
>  648: 44 00 48 00 l.jr r9
>  64c: 9c 21 00 30 l.addi r1,r1,0x30
>
> 00000650 <_main>:
>  650: 9c 21 ff c4 l.addi r1,r1,0xffffffc4
>  654: d4 01 10 04 l.sw 0x4(r1),r2
>  658: 9c 41 00 3c l.addi r2,r1,0x3c
>  65c: d4 01 48 00 l.sw 0x0(r1),r9
>  660: 07 ff fe e8 l.jal 200 <_uart_init>
>  664: 15 00 00 00 l.nop 0x0
>  668: 18 60 00 00 l.movhi r3,0x0
>  66c: a8 63 07 44 l.ori r3,r3,0x744
>  670: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3
>  674: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
>  678: 84 63 00 00 l.lwz r3,0x0(r3)
>  67c: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
>  680: 84 62 ff f4 l.lwz r3,0xfffffff4(r2)
>  684: d7 e2 1f fc l.sw 0xfffffffc(r2),r3
>  688: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
>  68c: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
>  690: 84 62 ff f0 l.lwz r3,0xfffffff0(r2)
>  694: 90 63 00 00 l.lbs r3,0x0(r3)
>  698: d7 e2 1f ec l.sw 0xffffffec(r2),r3
>  69c: 84 62 ff ec l.lwz r3,0xffffffec(r2)
>  6a0: bc 03 00 00 l.sfeqi r3,0x0
>  6a4: 10 00 00 13 l.bf 6f0 <_main+0xa0>
>  6a8: 15 00 00 00 l.nop 0x0
>  6ac: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
>  6b0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3
>  6b4: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
>  6b8: 90 63 00 00 l.lbs r3,0x0(r3)
>  6bc: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
>  6c0: 84 62 ff e4 l.lwz r3,0xffffffe4(r2)
>  6c4: 07 ff ff 59 l.jal 428 <_uart_putc>
>  6c8: 15 00 00 00 l.nop 0x0
>  6cc: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
>  6d0: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
>  6d4: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
>  6d8: 9c 63 00 01 l.addi r3,r3,0x1
>  6dc: d7 e2 1f dc l.sw 0xffffffdc(r2),r3
>  6e0: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
>  6e4: d7 e2 1f fc l.sw 0xfffffffc(r2),r3
>  6e8: 03 ff ff e8 l.j 688 <_main+0x38>
>  6ec: 15 00 00 00 l.nop 0x0
>  6f0: 07 ff ff ae l.jal 5a8 <_uart_getc>
>  6f4: 15 00 00 00 l.nop 0x0
>  6f8: d7 e2 5f d8 l.sw 0xffffffd8(r2),r11
>  6fc: 84 62 ff d8 l.lwz r3,0xffffffd8(r2)
>  700: 9c 63 00 01 l.addi r3,r3,0x1
>  704: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
>  708: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
>  70c: b8 63 00 18 l.slli r3,r3,0x18
>  710: d7 e2 1f cc l.sw 0xffffffcc(r2),r3
>  714: 84 62 ff cc l.lwz r3,0xffffffcc(r2)
>  718: b8 63 00 98 l.srai r3,r3,0x18
>  71c: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
>  720: 84 62 ff d0 l.lwz r3,0xffffffd0(r2)
>  724: 07 ff ff 41 l.jal 428 <_uart_putc>
>  728: 15 00 00 00 l.nop 0x0
>  72c: 03 ff ff f1 l.j 6f0 <_main+0xa0>
>  730: 15 00 00 00 l.nop 0x0
>  734: 85 21 00 00 l.lwz r9,0x0(r1)
>  738: 84 41 00 04 l.lwz r2,0x4(r1)
>  73c: 44 00 48 00 l.jr r9
>  740: 9c 21 00 3c l.addi r1,r1,0x3c
>
>
>
> ----- Original Message -----
> From: Robert Cragie<rcc@j...>
> To:
> Date: Thu Nov 22 11:30:49 CET 2007
> Subject: [openrisc] how to run hello world in on-chip ram?
>
> > Can you post the disassembly of your hello.or32 file?:
> >
> > or32-uclinux-objdump -d hello.or32
> >
> > That will give a clearer picture of where everything is.
> >
> > Robert
> >
> > Robert Cragie, Design Engineer
> >
> _____________________________________________________________
> __
> > Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> > http://www.jennic.com Tel: [phone]
> >
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc

_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[charlie yang]

You are right. the on_chip_ram address instantiated as:
altsyncram altsyncram_component (
        .wren_a (we),
        .clock0 (wb_clk_i),
        .byteena_a (be_i),
        .address_a (wb_adr_i[aw+1:2]), ****This should be point.
        .data_a (wb_dat_i),
             .q_a (wb_dat_o)
)

----- Original Message -----
From: Robert Cragie<rcc@j...>
To:
Date: Fri Nov 23 10:46:34 CET 2007
Subject: [openrisc] how to run hello world in on-chip ram?

> OK, I guess the Intelhex bit ended up being misleading. I have
> never
> actually attempted what you are doing. With respect to the
> addresses, again
> I guess that the address bus to the memory actually starts at
> address bit 2,
> with address bits 1 and 0 decoded for the byte lanes of 32-bit wide
> memory.
> Therefore it seems reasonable to me that the address *lines* will
> appear to
> be shifted by 2 as you state.
> Robert
> Robert Cragie, Design Engineer
>

_____________________________________________________________
__
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> http://www.jennic.com Tel: [phone]
>
_____________________________________________________________
__

> > -----Original Message-----
> > From: openrisc-bounces at opencores.org
> > [mailto:openrisc-bounces at opencores.org]On Behalf Of charlie
> yang
> > Sent: 23 November 2007 01:58
> > To: openrisc at opencores.org
> > Subject: Re: [openrisc] how to run hello world in on-chip ram?
> >
> >
> > Thanks Robert.
> > I find where is the problem ,but dont' know why.
> > When I use or32-uclinux-objcopy command to get the ram.hex,
> > the "_start" physical address in RAM is 0x100, and
> CPU cannot jump
> > there.
> > But if i use orp_soc/sw/utils/bin2hex to convert the hello.bin
> to
> > hello.hex
> > (it's not the intel hex format),then copy the content of
> hello.hex to
> > altera ram.hex, my hello-uart runs ok. But in this condition
> the physical
> > address of "_start" is 0x40 (right shift 2 bit than
> 0x100). These two
> > kinds of hex files come from the same hello.bin or hello.or32,
> why make
> > out the different start address?
> >
> >
> > The following is the file using "or32-uclinux-dump -d
> hello.or32":
> >
> >
> > hello.or32: file format elf32-or32
> >
> > Disassembly of section .vectors:
> >
> > 00000000 <_start-0x100>:
> > ...
> >
> > 00000100 <_start>:
> > 100: 18 20 00 00 l.movhi r1,0x0
> > 104: a8 21 0d 52 l.ori r1,r1,0xd52
> > 108: 9c 40 ff fd l.addi r2,r0,0xfffffffd
> > 10c: e0 21 10 03 l.and r1,r1,r2
> > 110: 18 40 00 00 l.movhi r2,0x0
> > 114: a8 42 06 50 l.ori r2,r2,0x650
> > 118: 44 00 10 00 l.jr r2
> > 11c: 9c 40 00 00 l.addi r2,r0,0x0
> >
> > 00000120 <___main>:
> > 120: 44 00 48 00 l.jr r9
> > 124: 15 00 00 00 l.nop 0x0
> > Disassembly of section .text:
> >
> > 00000200 <_uart_init>:
> > 200: 9c 21 ff 44 l.addi r1,r1,0xffffff44
> > 204: d4 01 10 00 l.sw 0x0(r1),r2
> > 208: 9c 41 00 bc l.addi r2,r1,0xbc
> > 20c: 18 60 90 00 l.movhi r3,0x9000
> > 210: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
> > 214: 84 82 ff f4 l.lwz r4,0xfffffff4(r2)
> > 218: a8 84 00 02 l.ori r4,r4,0x2
> > 21c: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4
> > 220: 9c 60 ff c7 l.addi r3,r0,0xffffffc7
> > 224: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
> > 228: 84 82 ff f0 l.lwz r4,0xfffffff0(r2)
> > 22c: db e2 27 ef l.sb 0xffffffef(r2),r4
> > 230: 8c 82 ff ef l.lbz r4,0xffffffef(r2)
> > 234: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
> > 238: d8 03 20 00 l.sb 0x0(r3),r4
> > 23c: 18 60 90 00 l.movhi r3,0x9000
> > 240: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
> > 244: 84 82 ff e4 l.lwz r4,0xffffffe4(r2)
> > 248: a8 84 00 01 l.ori r4,r4,0x1
> > 24c: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4
> > 250: 9c 60 00 00 l.addi r3,r0,0x0
> > 254: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
> > 258: 84 82 ff e0 l.lwz r4,0xffffffe0(r2)
> > 25c: db e2 27 df l.sb 0xffffffdf(r2),r4
> > 260: 8c 82 ff df l.lbz r4,0xffffffdf(r2)
> > 264: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
> > 268: d8 03 20 00 l.sb 0x0(r3),r4
> > 26c: 18 60 90 00 l.movhi r3,0x9000
> > 270: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
> > 274: 84 82 ff d4 l.lwz r4,0xffffffd4(r2)
> > 278: a8 84 00 03 l.ori r4,r4,0x3
> > 27c: d7 e2 27 d8 l.sw 0xffffffd8(r2),r4
> > 280: 9c 60 00 03 l.addi r3,r0,0x3
> > 284: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
> > 288: 84 82 ff d0 l.lwz r4,0xffffffd0(r2)
> > 28c: db e2 27 cf l.sb 0xffffffcf(r2),r4
> > 290: 8c 82 ff cf l.lbz r4,0xffffffcf(r2) > 294: 84 62 ff
> d8 l.lwz r3,0xffffffd8(r2) > 298: d8 03 20 00 l.sb 0x0(r3),r4
> > 29c: 9c 60 00 41 l.addi r3,r0,0x41 > 2a0: d7 e2 1f c8
> l.sw 0xffffffc8(r2),r3 > 2a4: 84 82 ff c8 l.lwz
> r4,0xffffffc8(r2) > 2a8: d7 e2 27 fc l.sw 0xfffffffc(r2),r4
> > 2ac: 18 60 90 00 l.movhi r3,0x9000 > 2b0: d7 e2 1f c0
> l.sw 0xffffffc0(r2),r3 > 2b4: 84 82 ff c0 l.lwz
> r4,0xffffffc0(r2) > 2b8: a8 84 00 03 l.ori r4,r4,0x3 >
> 2bc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4 > 2c0: 18 60 90 00
> l.movhi r3,0x9000 > 2c4: d7 e2 1f b8 l.sw 0xffffffb8

(r2),r3
> > 2c8: 84 82 ff b8 l.lwz r4,0xffffffb8(r2) > 2cc: a8 84 00
> 03 l.ori r4,r4,0x3 > 2d0: d7 e2 27 bc l.sw 0xffffffbc
(r2),r4
> > 2d4: 84 62 ff bc l.lwz r3,0xffffffbc(r2) > 2d8: 8c 63 00
> 00 l.lbz r3,0x0(r3) > 2dc: db e2 1f b7 l.sb 0xffffffb7
(r2),r3
> > 2e0: 9c 60 ff 80 l.addi r3,r0,0xffffff80 > 2e4: 8c 82 ff
> b7 l.lbz r4,0xffffffb7(r2) > 2e8: e0 64 18 04 l.or r3,r4,r3
> > 2ec: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 > 2f0: 84 82 ff b0
> l.lwz r4,0xffffffb0(r2) > 2f4: db e2 27 af l.sb
> 0xffffffaf(r2),r4 > 2f8: 8c 82 ff af l.lbz r4,0xffffffaf(r2)
> > 2fc: 84 62 ff c4 l.lwz r3,0xffffffc4(r2) > 300: d8 03 20
> 00 l.sb 0x0(r3),r4 > 304: 18 60 90 00 l.movhi
r3,0x9000 >

> 308: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 > 30c: 84 82 ff fc
> l.lwz r4,0xfffffffc(r2) > 310: d7 e2 27 a4 l.sw
> 0xffffffa4(r2),r4 > 314: 9c 60 ff ff l.addi r3,r0,0xffffffff
> > 318: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3 > 31c: 84 82 ff 9c
> l.lwz r4,0xffffff9c(r2) > 320: db e2 27 a3 l.sb
> 0xffffffa3(r2),r4 > 324: 84 62 ff a4 l.lwz r3,0xffffffa4(r2)
> > 328: db e2 1f 9b l.sb 0xffffff9b(r2),r3 > 32c: 8c 82 ff 9b
> l.lbz r4,0xffffff9b(r2) > 330: 8c 62 ff a3 l.lbz
> r3,0xffffffa3(r2) > 334: e0 84 18 03 l.and r4,r4,r3 >
> 338: d7 e2 27 94 l.sw 0xffffff94(r2),r4 > 33c: 84 82 ff 94
> l.lwz r4,0xffffff94(r2) > 340: db e2 27 93 l.sb
> 0xffffff93(r2),r4 > 344: 8c 82 ff 93 l.lbz r4,0xffffff93(r2)
> > 348: 84 62 ff a8 l.lwz r3,0xffffffa8(r2) > 34c: d8 03 20
> 00 l.sb 0x0(r3),r4 > 350: 18 60 90 00 l.movhi

r3,0x9000 >
> 354: d7 e2 1f 88 l.sw 0xffffff88(r2),r3 > 358: 84 82 ff 88
> l.lwz r4,0xffffff88(r2) > 35c: a8 84 00 01 l.ori r4,r4,0x1
> > 360: d7 e2 27 8c l.sw 0xffffff8c(r2),r4 > 364: 84 62 ff fc
> l.lwz r3,0xfffffffc(r2) > 368: d7 e2 1f 80 l.sw
> 0xffffff80(r2),r3 > 36c: 84 82 ff 80 l.lwz r4,0xffffff80(r2)
> > 370: b8 84 00 88 l.srai r4,r4,0x8 > 374: d7 e2 27 84
        l.sw

> 0xffffff84(r2),r4 > 378: 9c 60 ff ff l.addi r3,r0,0xffffffff
> > 37c: d7 e2 1f 78 l.sw 0xffffff78(r2),r3 > 380: 84 82 ff 78
> l.lwz r4,0xffffff78(r2) > 384: db e2 27 7f l.sb
> 0xffffff7f(r2),r4 > 388: 84 62 ff 84 l.lwz r3,0xffffff84(r2)
> > 38c: db e2 1f 77 l.sb 0xffffff77(r2),r3 > 390: 8c 82 ff 77
> l.lbz r4,0xffffff77(r2) > 394: 8c 62 ff 7f l.lbz
> r3,0xffffff7f(r2) > 398: e0 84 18 03 l.and r4,r4,r3 >
> 39c: d7 e2 27 70 l.sw 0xffffff70(r2),r4 > 3a0: 84 82 ff 70
> l.lwz r4,0xffffff70(r2) > 3a4: db e2 27 6f l.sb
> 0xffffff6f(r2),r4 > 3a8: 8c 82 ff 6f l.lbz r4,0xffffff6f(r2)
> > 3ac: 84 62 ff 8c l.lwz r3,0xffffff8c(r2) > 3b0: d8 03 20
> 00 l.sb 0x0(r3),r4 > 3b4: 18 60 90 00 l.movhi

r3,0x9000 >
> 3b8: d7 e2 1f 64 l.sw 0xffffff64(r2),r3 > 3bc: 84 82 ff 64
> l.lwz r4,0xffffff64(r2) > 3c0: a8 84 00 03 l.ori r4,r4,0x3
> > 3c4: d7 e2 27 68 l.sw 0xffffff68(r2),r4 > 3c8: 18 60 90 00
> l.movhi r3,0x9000 > 3cc: d7 e2 1f 5c l.sw 0xffffff5c
(r2),r3
> > 3d0: 84 82 ff 5c l.lwz r4,0xffffff5c(r2) > 3d4: a8 84 00
> 03 l.ori r4,r4,0x3 > 3d8: d7 e2 27 60 l.sw 0xffffff60
(r2),r4
> > 3dc: 9c 60 00 7f l.addi r3,r0,0x7f > 3e0: d7 e2 1f 54
> l.sw 0xffffff54(r2),r3 > 3e4: 84 82 ff 54 l.lwz
> r4,0xffffff54(r2) > 3e8: db e2 27 5b l.sb 0xffffff5b(r2),r4
> > 3ec: 84 62 ff 60 l.lwz r3,0xffffff60(r2) > 3f0: 8c 63 00
> 00 l.lbz r3,0x0(r3) > 3f4: db e2 1f 53 l.sb 0xffffff53
(r2),r3
> > 3f8: 8c 82 ff 53 l.lbz r4,0xffffff53(r2) > 3fc: 8c 62 ff
> 5b l.lbz r3,0xffffff5b(r2) > 400: e0 84 18 03 l.and r4,r4,r3
> > 404: d7 e2 27 4c l.sw 0xffffff4c(r2),r4 > 408: 84 82 ff 4c
> l.lwz r4,0xffffff4c(r2) > 40c: db e2 27 4b l.sb
> 0xffffff4b(r2),r4 > 410: 8c 82 ff 4b l.lbz r4,0xffffff4b(r2)
> > 414: 84 62 ff 68 l.lwz r3,0xffffff68(r2) > 418: d8 03 20
> 00 l.sb 0x0(r3),r4 > 41c: 84 41 00 00 l.lwz r2,0x0
(r1) >
> 420: 44 00 48 00 l.jr r9 > 424: 9c 21 00 bc l.addi
r1,r1,0xbc
> > > 00000428 <_uart_putc>: > 428: 9c 21 ff 9c
> l.addi r1,r1,0xffffff9c > 42c: d4 01 10 00 l.sw 0x0(r1),r2
> > 430: 9c 41 00 64 l.addi r2,r1,0x64 > 434: d7 e2 1f f8
> l.sw 0xfffffff8(r2),r3 > 438: 84 62 ff f8 l.lwz
> r3,0xfffffff8(r2) > 43c: db e2 1f f7 l.sb 0xfffffff7(r2),r3
> > 440: 8c 82 ff f7 l.lbz r4,0xfffffff7(r2) > 444: db e2 27
> ff l.sb 0xffffffff(r2),r4 > 448: 18 60 90 00 l.movhi
r3,0x9000
> > 44c: d7 e2 1f ec l.sw 0xffffffec(r2),r3 > 450: 84 82 ff ec
> l.lwz r4,0xffffffec(r2) > 454: a8 84 00 05 l.ori r4,r4,0x5
> > 458: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4 > 45c: 84 62 ff f0
> l.lwz r3,0xfffffff0(r2) > 460: 8c 63 00 00 l.lbz r3,0x0(r3)
> > 464: db e2 1f eb l.sb 0xffffffeb(r2),r3 > 468: 8c 82 ff eb
> l.lbz r4,0xffffffeb(r2) > 46c: db e2 27 fe l.sb
> 0xfffffffe(r2),r4 > 470: 8c 62 ff fe l.lbz r3,0xfffffffe(r2)
> > 474: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 > 478: 84 82 ff e4
> l.lwz r4,0xffffffe4(r2) > 47c: a4 84 00 20 l.andi
r4,r4,0x20
> > 480: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 > 484: 84 62 ff e0
> l.lwz r3,0xffffffe0(r2) > 488: bc 23 00 00 l.sfnei r3,0x0 >
> 48c: 10 00 00 04 l.bf 49c <_uart_putc+0x74> > 490: 15
00
> 00 00 l.nop 0x0 > 494: 03 ff ff ed l.j 448
> <_uart_putc+0x20> > 498: 15 00 00 00 l.nop 0x0 >
> 49c: 18 80 90 00 l.movhi r4,0x9000 > 4a0: d7 e2 27 dc
        l.sw
> 0xffffffdc(r2),r4 > 4a4: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
> > 4a8: db e2 1f db l.sb 0xffffffdb(r2),r3 > 4ac: 8c 62 ff db
> l.lbz r3,0xffffffdb(r2) > 4b0: 84 82 ff dc l.lwz
> r4,0xffffffdc(r2) > 4b4: d8 04 18 00 l.sb 0x0(r4),r3 >
> 4b8: 90 82 ff ff l.lbs r4,0xffffffff(r2) > 4bc: d7 e2 27 d4
> l.sw 0xffffffd4(r2),r4 > 4c0: 84 62 ff d4 l.lwz
> r3,0xffffffd4(r2) > 4c4: bc 23 00 0a l.sfnei r3,0xa >
> 4c8: 10 00 00 20 l.bf 548 <_uart_putc+0x120> > 4cc: 15
00

> 00 00 l.nop 0x0 > 4d0: 18 80 90 00 l.movhi r4,0x9000 >
> 4d4: d7 e2 27 cc l.sw 0xffffffcc(r2),r4 > 4d8: 84 62 ff cc
> l.lwz r3,0xffffffcc(r2) > 4dc: a8 63 00 05 l.ori r3,r3,0x5
> > 4e0: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3 > 4e4: 84 82 ff d0
> l.lwz r4,0xffffffd0(r2) > 4e8: 8c 84 00 00 l.lbz r4,0x0(r4)
> > 4ec: db e2 27 cb l.sb 0xffffffcb(r2),r4 > 4f0: 8c 62 ff cb
> l.lbz r3,0xffffffcb(r2) > 4f4: db e2 1f fe l.sb
> 0xfffffffe(r2),r3 > 4f8: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
> > 4fc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4 > 500: 84 62 ff c4
> l.lwz r3,0xffffffc4(r2) > 504: a4 63 00 20 l.andi

r3,r3,0x20
> > 508: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3 > 50c: 84 82 ff c0
> l.lwz r4,0xffffffc0(r2) > 510: bc 24 00 00 l.sfnei r4,0x0 >
> 514: 10 00 00 04 l.bf 524 <_uart_putc+0xfc> > 518: 15
00
> 00 00 l.nop 0x0 > 51c: 03 ff ff ed l.j 4d0
> <_uart_putc+0xa8> > 520: 15 00 00 00 l.nop 0x0 >
> 524: 18 60 90 00 l.movhi r3,0x9000 > 528: d7 e2 1f bc
        l.sw
> 0xffffffbc(r2),r3 > 52c: 9c 80 00 0d l.addi r4,r0,0xd >
> 530: d7 e2 27 b8 l.sw 0xffffffb8(r2),r4 > 534: 84 62 ff b8
> l.lwz r3,0xffffffb8(r2) > 538: db e2 1f b7 l.sb
> 0xffffffb7(r2),r3 > 53c: 8c 62 ff b7 l.lbz r3,0xffffffb7(r2)
> > 540: 84 82 ff bc l.lwz r4,0xffffffbc(r2) > 544: d8 04 18
> 00 l.sb 0x0(r4),r3 > 548: 18 80 90 00 l.movhi
r4,0x9000 >
> 54c: d7 e2 27 ac l.sw 0xffffffac(r2),r4 > 550: 84 62 ff ac
> l.lwz r3,0xffffffac(r2) > 554: a8 63 00 05 l.ori r3,r3,0x5
> > 558: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 > 55c: 84 82 ff b0
> l.lwz r4,0xffffffb0(r2) > 560: 8c 84 00 00 l.lbz r4,0x0(r4)
> > 564: db e2 27 ab l.sb 0xffffffab(r2),r4 > 568: 8c 62 ff ab
> l.lbz r3,0xffffffab(r2) > 56c: db e2 1f fe l.sb
> 0xfffffffe(r2),r3 > 570: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
> > 574: d7 e2 27 a4 l.sw 0xffffffa4(r2),r4 > 578: 84 62 ff a4
> l.lwz r3,0xffffffa4(r2) > 57c: a4 63 00 60 l.andi
r3,r3,0x60
> > 580: d7 e2 1f a0 l.sw 0xffffffa0(r2),r3 > 584: 84 82 ff a0
> l.lwz r4,0xffffffa0(r2) > 588: bc 04 00 60 l.sfeqi r4,0x60
> > 58c: 10 00 00 04 l.bf 59c <_uart_putc+0x174> >
> 590: 15 00 00 00 l.nop 0x0 > 594: 03 ff ff ed l.j
548
> <_uart_putc+0x120> > 598: 15 00 00 00 l.nop 0x0 >
> 59c: 84 41 00 00 l.lwz r2,0x0(r1) > 5a0: 44 00 48 00
        l.jr r9
> > 5a4: 9c 21 00 64 l.addi r1,r1,0x64 > > 000005a8
> <_uart_getc>: > 5a8: 9c 21 ff d0 l.addi r1,r1,0xffffffd0
> > 5ac: d4 01 10 00 l.sw 0x0(r1),r2 > 5b0: 9c 41 00 30
> l.addi r2,r1,0x30 > 5b4: 18 60 90 00 l.movhi
r3,0x9000 >

> 5b8: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 > 5bc: 84 62 ff f0
> l.lwz r3,0xfffffff0(r2) > 5c0: a8 63 00 05 l.ori r3,r3,0x5
> > 5c4: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 > 5c8: 84 62 ff f4
> l.lwz r3,0xfffffff4(r2) > 5cc: 8c 63 00 00 l.lbz r3,0x0(r3)
> > 5d0: db e2 1f ef l.sb 0xffffffef(r2),r3 > 5d4: 8c 62 ff ef
> l.lbz r3,0xffffffef(r2) > 5d8: db e2 1f ff l.sb
> 0xffffffff(r2),r3 > 5dc: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
> > 5e0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 > 5e4: 84 62 ff e8
> l.lwz r3,0xffffffe8(r2) > 5e8: ac 63 00 01 l.xori r3,r3,0x1
> > 5ec: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 > 5f0: 84 62 ff e4
> l.lwz r3,0xffffffe4(r2) > 5f4: a4 63 00 01 l.andi r3,r3,0x1
> > 5f8: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 > 5fc: 84 62 ff e0
> l.lwz r3,0xffffffe0(r2) > 600: bc 03 00 00 l.sfeqi r3,0x0 >
> 604: 10 00 00 04 l.bf 614 <_uart_getc+0x6c> > 608: 15

00
> 00 00 l.nop 0x0 > 60c: 03 ff ff ea l.j 5b4
> <_uart_getc+0xc> > 610: 15 00 00 00 l.nop 0x0 >
> 614: 18 60 90 00 l.movhi r3,0x9000 > 618: d7 e2 1f dc
        l.sw
> 0xffffffdc(r2),r3 > 61c: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
> > 620: 8c 63 00 00 l.lbz r3,0x0(r3) > 624: db e2 1f db
        l.sb
> 0xffffffdb(r2),r3 > 628: 8c 62 ff db l.lbz r3,0xffffffdb(r2)
> > 62c: db e2 1f fe l.sb 0xfffffffe(r2),r3 > 630: 90 62 ff fe
> l.lbs r3,0xfffffffe(r2) > 634: d7 e2 1f d4 l.sw
> 0xffffffd4(r2),r3 > 638: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
> > 63c: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 > 640: 85 62 ff f8
> l.lwz r11,0xfffffff8(r2) > 644: 84 41 00 00 l.lwz
r2,0x0(r1)
> > 648: 44 00 48 00 l.jr r9 > 64c: 9c 21 00 30 l.addi
> r1,r1,0x30 > > 00000650 <_main>: > 650: 9c 21 ff c4
> l.addi r1,r1,0xffffffc4 > 654: d4 01 10 04 l.sw 0x4(r1),r2
> > 658: 9c 41 00 3c l.addi r2,r1,0x3c > 65c: d4 01 48 00
> l.sw 0x0(r1),r9 > 660: 07 ff fe e8 l.jal 200
> <_uart_init> > 664: 15 00 00 00 l.nop 0x0 > 668: 18
60
> 00 00 l.movhi r3,0x0 > 66c: a8 63 07 44 l.ori
r3,r3,0x744 >
> 670: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 > 674: 84 62 ff f8
> l.lwz r3,0xfffffff8(r2) > 678: 84 63 00 00 l.lwz r3,0x0
(r3)
> > 67c: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 > 680: 84 62 ff f4
> l.lwz r3,0xfffffff4(r2) > 684: d7 e2 1f fc l.sw
> 0xfffffffc(r2),r3 > 688: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
> > 68c: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 > 690: 84 62 ff f0
> l.lwz r3,0xfffffff0(r2) > 694: 90 63 00 00 l.lbs r3,0x0(r3)
> > 698: d7 e2 1f ec l.sw 0xffffffec(r2),r3 > 69c: 84 62 ff ec
> l.lwz r3,0xffffffec(r2) > 6a0: bc 03 00 00 l.sfeqi r3,0x0 >
> 6a4: 10 00 00 13 l.bf 6f0 <_main+0xa0> > 6a8: 15
00 00 00
> l.nop 0x0 > 6ac: 84 62 ff fc l.lwz r3,0xfffffffc(r2) >
> 6b0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 > 6b4: 84 62 ff e8
> l.lwz r3,0xffffffe8(r2) > 6b8: 90 63 00 00 l.lbs r3,0x0(r3)
> > 6bc: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 > 6c0: 84 62 ff e4
> l.lwz r3,0xffffffe4(r2) > 6c4: 07 ff ff 59 l.jal 428
> <_uart_putc> > 6c8: 15 00 00 00 l.nop 0x0 > 6cc: 84
62
> ff fc l.lwz r3,0xfffffffc(r2) > 6d0: d7 e2 1f e0 l.sw
> 0xffffffe0(r2),r3 > 6d4: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
> > 6d8: 9c 63 00 01 l.addi r3,r3,0x1 > 6dc: d7 e2 1f dc
        l.sw
> 0xffffffdc(r2),r3 > 6e0: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
> > 6e4: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 > 6e8: 03 ff ff e8
> l.j 688 <_main+0x38> > 6ec: 15 00 00 00 l.nop 0x0 >
> 6f0: 07 ff ff ae l.jal 5a8 <_uart_getc> > 6f4: 15
00 00
> 00 l.nop 0x0 > 6f8: d7 e2 5f d8 l.sw 0xffffffd8(r2),r11 >
> 6fc: 84 62 ff d8 l.lwz r3,0xffffffd8(r2) > 700: 9c 63 00 01
> l.addi r3,r3,0x1 > 704: d7 e2 1f d4 l.sw 0xffffffd4
(r2),r3
> > 708: 84 62 ff d4 l.lwz r3,0xffffffd4(r2) > 70c: b8 63 00
> 18 l.slli r3,r3,0x18 > 710: d7 e2 1f cc l.sw 0xffffffcc
(r2),r3
> > 714: 84 62 ff cc l.lwz r3,0xffffffcc(r2) > 718: b8 63 00
> 98 l.srai r3,r3,0x18 > 71c: d7 e2 1f d0 l.sw 0xffffffd0
(r2),r3
> > 720: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) > 724: 07 ff ff
> 41 l.jal 428 <_uart_putc> > 728: 15 00 00 00 l.nop
0x0
> > 72c: 03 ff ff f1 l.j 6f0 <_main+0xa0> > 730: 15 00
> 00 00 l.nop 0x0 > 734: 85 21 00 00 l.lwz r9,0x0(r1) >
> 738: 84 41 00 04 l.lwz r2,0x4(r1) > 73c: 44 00 48 00
        l.jr r9

> > 740: 9c 21 00 3c l.addi r1,r1,0x3c > > > > -----
> Original Message ----- > From: Robert Cragie<rcc at j...>
> > To: > Date: Thu Nov 22 11:30:49 CET 2007 > Subject:
> [openrisc] how to run hello world in on-chip ram? > > >
> Can you post the disassembly of your hello.or32 file?: > >
> > > or32-uclinux-objdump -d hello.or32 > > > >
> That will give a clearer picture of where everything is. > >
> > > Robert > > > > Robert Cragie, Design Engineer
> > > >
>

_____________________________________________________________
 >
> __ > > Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> > > http://www.jennic.com Tel: [phone] > >
> > _______________________________________________ >
> http://www.opencores.org/mailman/listinfo/openrisc 
>
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[beking]

hi, charlie yang:
now,i also do the same thing as you for "hello world" appearing on my dev_board(cycloneII),and now i deal with hardware(or1200 uart debud onchip_ram) according to hardware toturial,but some error coming!do you know how i do ?
quenstions as follows:
1:according to the author ,adjust"or1200_pc.v",but there is no this file in source files~~~
2:on_chip_ram,how do i do ?
3:when compiling,erros....i dont resolve...please help me ,,,i am real real need it ...
thank you advanced!!!!!
can you give me some advise?

charlie yang wrote:

You are right. the on_chip_ram address instantiated as:
altsyncram altsyncram_component (
        .wren_a (we),
        .clock0 (wb_clk_i),
        .byteena_a (be_i),
        .address_a (wb_adr_i[aw+1:2]), ****This should be point.
        .data_a (wb_dat_i),
             .q_a (wb_dat_o)
)

----- Original Message -----
From: Robert Cragie<rcc@j...>
To:
Date: Fri Nov 23 10:46:34 CET 2007
Subject: [openrisc] how to run hello world in on-chip ram?

> OK, I guess the Intelhex bit ended up being misleading. I have
> never
> actually attempted what you are doing. With respect to the
> addresses, again
> I guess that the address bus to the memory actually starts at
> address bit 2,
> with address bits 1 and 0 decoded for the byte lanes of 32-bit wide
> memory.
> Therefore it seems reasonable to me that the address *lines* will
> appear to
> be shifted by 2 as you state.
> Robert
> Robert Cragie, Design Engineer
>
_____________________________________________________________
__
> Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> http://www.jennic.com Tel: [phone]
>
_____________________________________________________________
__
> > -----Original Message-----
> > From: openrisc-bounces at opencores.org
> > [mailto:openrisc-bounces at opencores.org]On Behalf Of charlie
> yang
> > Sent: 23 November 2007 01:58
> > To: openrisc at opencores.org
> > Subject: Re: [openrisc] how to run hello world in on-chip ram?
> >
> >
> > Thanks Robert.
> > I find where is the problem ,but dont' know why.
> > When I use or32-uclinux-objcopy command to get the ram.hex,
> > the "_start" physical address in RAM is 0x100, and
> CPU cannot jump
> > there.
> > But if i use orp_soc/sw/utils/bin2hex to convert the hello.bin
> to
> > hello.hex
> > (it's not the intel hex format),then copy the content of
> hello.hex to
> > altera ram.hex, my hello-uart runs ok. But in this condition
> the physical
> > address of "_start" is 0x40 (right shift 2 bit than
> 0x100). These two
> > kinds of hex files come from the same hello.bin or hello.or32,
> why make
> > out the different start address?
> >
> >
> > The following is the file using "or32-uclinux-dump -d
> hello.or32":
> >
> >
> > hello.or32: file format elf32-or32
> >
> > Disassembly of section .vectors:
> >
> > 00000000 <_start-0x100>:
> > ...
> >
> > 00000100 <_start>:
> > 100: 18 20 00 00 l.movhi r1,0x0
> > 104: a8 21 0d 52 l.ori r1,r1,0xd52
> > 108: 9c 40 ff fd l.addi r2,r0,0xfffffffd
> > 10c: e0 21 10 03 l.and r1,r1,r2
> > 110: 18 40 00 00 l.movhi r2,0x0
> > 114: a8 42 06 50 l.ori r2,r2,0x650
> > 118: 44 00 10 00 l.jr r2
> > 11c: 9c 40 00 00 l.addi r2,r0,0x0
> >
> > 00000120 <___main>:
> > 120: 44 00 48 00 l.jr r9
> > 124: 15 00 00 00 l.nop 0x0
> > Disassembly of section .text:
> >
> > 00000200 <_uart_init>:
> > 200: 9c 21 ff 44 l.addi r1,r1,0xffffff44
> > 204: d4 01 10 00 l.sw 0x0(r1),r2
> > 208: 9c 41 00 bc l.addi r2,r1,0xbc
> > 20c: 18 60 90 00 l.movhi r3,0x9000
> > 210: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
> > 214: 84 82 ff f4 l.lwz r4,0xfffffff4(r2)
> > 218: a8 84 00 02 l.ori r4,r4,0x2
> > 21c: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4
> > 220: 9c 60 ff c7 l.addi r3,r0,0xffffffc7
> > 224: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
> > 228: 84 82 ff f0 l.lwz r4,0xfffffff0(r2)
> > 22c: db e2 27 ef l.sb 0xffffffef(r2),r4
> > 230: 8c 82 ff ef l.lbz r4,0xffffffef(r2)
> > 234: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
> > 238: d8 03 20 00 l.sb 0x0(r3),r4
> > 23c: 18 60 90 00 l.movhi r3,0x9000
> > 240: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3
> > 244: 84 82 ff e4 l.lwz r4,0xffffffe4(r2)
> > 248: a8 84 00 01 l.ori r4,r4,0x1
> > 24c: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4
> > 250: 9c 60 00 00 l.addi r3,r0,0x0
> > 254: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3
> > 258: 84 82 ff e0 l.lwz r4,0xffffffe0(r2)
> > 25c: db e2 27 df l.sb 0xffffffdf(r2),r4
> > 260: 8c 82 ff df l.lbz r4,0xffffffdf(r2)
> > 264: 84 62 ff e8 l.lwz r3,0xffffffe8(r2)
> > 268: d8 03 20 00 l.sb 0x0(r3),r4
> > 26c: 18 60 90 00 l.movhi r3,0x9000
> > 270: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3
> > 274: 84 82 ff d4 l.lwz r4,0xffffffd4(r2)
> > 278: a8 84 00 03 l.ori r4,r4,0x3
> > 27c: d7 e2 27 d8 l.sw 0xffffffd8(r2),r4
> > 280: 9c 60 00 03 l.addi r3,r0,0x3
> > 284: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3
> > 288: 84 82 ff d0 l.lwz r4,0xffffffd0(r2)
> > 28c: db e2 27 cf l.sb 0xffffffcf(r2),r4
> > 290: 8c 82 ff cf l.lbz r4,0xffffffcf(r2) > 294: 84 62 ff
> d8 l.lwz r3,0xffffffd8(r2) > 298: d8 03 20 00 l.sb 0x0(r3),r4
> > 29c: 9c 60 00 41 l.addi r3,r0,0x41 > 2a0: d7 e2 1f c8
> l.sw 0xffffffc8(r2),r3 > 2a4: 84 82 ff c8 l.lwz
> r4,0xffffffc8(r2) > 2a8: d7 e2 27 fc l.sw 0xfffffffc(r2),r4
> > 2ac: 18 60 90 00 l.movhi r3,0x9000 > 2b0: d7 e2 1f c0
> l.sw 0xffffffc0(r2),r3 > 2b4: 84 82 ff c0 l.lwz
> r4,0xffffffc0(r2) > 2b8: a8 84 00 03 l.ori r4,r4,0x3 >
> 2bc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4 > 2c0: 18 60 90 00
> l.movhi r3,0x9000 > 2c4: d7 e2 1f b8 l.sw 0xffffffb8
(r2),r3
> > 2c8: 84 82 ff b8 l.lwz r4,0xffffffb8(r2) > 2cc: a8 84 00
> 03 l.ori r4,r4,0x3 > 2d0: d7 e2 27 bc l.sw 0xffffffbc
(r2),r4
> > 2d4: 84 62 ff bc l.lwz r3,0xffffffbc(r2) > 2d8: 8c 63 00
> 00 l.lbz r3,0x0(r3) > 2dc: db e2 1f b7 l.sb 0xffffffb7
(r2),r3
> > 2e0: 9c 60 ff 80 l.addi r3,r0,0xffffff80 > 2e4: 8c 82 ff
> b7 l.lbz r4,0xffffffb7(r2) > 2e8: e0 64 18 04 l.or r3,r4,r3
> > 2ec: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 > 2f0: 84 82 ff b0
> l.lwz r4,0xffffffb0(r2) > 2f4: db e2 27 af l.sb
> 0xffffffaf(r2),r4 > 2f8: 8c 82 ff af l.lbz r4,0xffffffaf(r2)
> > 2fc: 84 62 ff c4 l.lwz r3,0xffffffc4(r2) > 300: d8 03 20
> 00 l.sb 0x0(r3),r4 > 304: 18 60 90 00 l.movhi
r3,0x9000 >
> 308: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 > 30c: 84 82 ff fc
> l.lwz r4,0xfffffffc(r2) > 310: d7 e2 27 a4 l.sw
> 0xffffffa4(r2),r4 > 314: 9c 60 ff ff l.addi r3,r0,0xffffffff
> > 318: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3 > 31c: 84 82 ff 9c
> l.lwz r4,0xffffff9c(r2) > 320: db e2 27 a3 l.sb
> 0xffffffa3(r2),r4 > 324: 84 62 ff a4 l.lwz r3,0xffffffa4(r2)
> > 328: db e2 1f 9b l.sb 0xffffff9b(r2),r3 > 32c: 8c 82 ff 9b
> l.lbz r4,0xffffff9b(r2) > 330: 8c 62 ff a3 l.lbz
> r3,0xffffffa3(r2) > 334: e0 84 18 03 l.and r4,r4,r3 >
> 338: d7 e2 27 94 l.sw 0xffffff94(r2),r4 > 33c: 84 82 ff 94
> l.lwz r4,0xffffff94(r2) > 340: db e2 27 93 l.sb
> 0xffffff93(r2),r4 > 344: 8c 82 ff 93 l.lbz r4,0xffffff93(r2)
> > 348: 84 62 ff a8 l.lwz r3,0xffffffa8(r2) > 34c: d8 03 20
> 00 l.sb 0x0(r3),r4 > 350: 18 60 90 00 l.movhi
r3,0x9000 >
> 354: d7 e2 1f 88 l.sw 0xffffff88(r2),r3 > 358: 84 82 ff 88
> l.lwz r4,0xffffff88(r2) > 35c: a8 84 00 01 l.ori r4,r4,0x1
> > 360: d7 e2 27 8c l.sw 0xffffff8c(r2),r4 > 364: 84 62 ff fc
> l.lwz r3,0xfffffffc(r2) > 368: d7 e2 1f 80 l.sw
> 0xffffff80(r2),r3 > 36c: 84 82 ff 80 l.lwz r4,0xffffff80(r2)
> > 370: b8 84 00 88 l.srai r4,r4,0x8 > 374: d7 e2 27 84
        l.sw
> 0xffffff84(r2),r4 > 378: 9c 60 ff ff l.addi r3,r0,0xffffffff
> > 37c: d7 e2 1f 78 l.sw 0xffffff78(r2),r3 > 380: 84 82 ff 78
> l.lwz r4,0xffffff78(r2) > 384: db e2 27 7f l.sb
> 0xffffff7f(r2),r4 > 388: 84 62 ff 84 l.lwz r3,0xffffff84(r2)
> > 38c: db e2 1f 77 l.sb 0xffffff77(r2),r3 > 390: 8c 82 ff 77
> l.lbz r4,0xffffff77(r2) > 394: 8c 62 ff 7f l.lbz
> r3,0xffffff7f(r2) > 398: e0 84 18 03 l.and r4,r4,r3 >
> 39c: d7 e2 27 70 l.sw 0xffffff70(r2),r4 > 3a0: 84 82 ff 70
> l.lwz r4,0xffffff70(r2) > 3a4: db e2 27 6f l.sb
> 0xffffff6f(r2),r4 > 3a8: 8c 82 ff 6f l.lbz r4,0xffffff6f(r2)
> > 3ac: 84 62 ff 8c l.lwz r3,0xffffff8c(r2) > 3b0: d8 03 20
> 00 l.sb 0x0(r3),r4 > 3b4: 18 60 90 00 l.movhi
r3,0x9000 >
> 3b8: d7 e2 1f 64 l.sw 0xffffff64(r2),r3 > 3bc: 84 82 ff 64
> l.lwz r4,0xffffff64(r2) > 3c0: a8 84 00 03 l.ori r4,r4,0x3
> > 3c4: d7 e2 27 68 l.sw 0xffffff68(r2),r4 > 3c8: 18 60 90 00
> l.movhi r3,0x9000 > 3cc: d7 e2 1f 5c l.sw 0xffffff5c
(r2),r3
> > 3d0: 84 82 ff 5c l.lwz r4,0xffffff5c(r2) > 3d4: a8 84 00
> 03 l.ori r4,r4,0x3 > 3d8: d7 e2 27 60 l.sw 0xffffff60
(r2),r4
> > 3dc: 9c 60 00 7f l.addi r3,r0,0x7f > 3e0: d7 e2 1f 54
> l.sw 0xffffff54(r2),r3 > 3e4: 84 82 ff 54 l.lwz
> r4,0xffffff54(r2) > 3e8: db e2 27 5b l.sb 0xffffff5b(r2),r4
> > 3ec: 84 62 ff 60 l.lwz r3,0xffffff60(r2) > 3f0: 8c 63 00
> 00 l.lbz r3,0x0(r3) > 3f4: db e2 1f 53 l.sb 0xffffff53
(r2),r3
> > 3f8: 8c 82 ff 53 l.lbz r4,0xffffff53(r2) > 3fc: 8c 62 ff
> 5b l.lbz r3,0xffffff5b(r2) > 400: e0 84 18 03 l.and r4,r4,r3
> > 404: d7 e2 27 4c l.sw 0xffffff4c(r2),r4 > 408: 84 82 ff 4c
> l.lwz r4,0xffffff4c(r2) > 40c: db e2 27 4b l.sb
> 0xffffff4b(r2),r4 > 410: 8c 82 ff 4b l.lbz r4,0xffffff4b(r2)
> > 414: 84 62 ff 68 l.lwz r3,0xffffff68(r2) > 418: d8 03 20
> 00 l.sb 0x0(r3),r4 > 41c: 84 41 00 00 l.lwz r2,0x0
(r1) >
> 420: 44 00 48 00 l.jr r9 > 424: 9c 21 00 bc l.addi
r1,r1,0xbc
> > > 00000428 <_uart_putc>: > 428: 9c 21 ff 9c
> l.addi r1,r1,0xffffff9c > 42c: d4 01 10 00 l.sw 0x0(r1),r2
> > 430: 9c 41 00 64 l.addi r2,r1,0x64 > 434: d7 e2 1f f8
> l.sw 0xfffffff8(r2),r3 > 438: 84 62 ff f8 l.lwz
> r3,0xfffffff8(r2) > 43c: db e2 1f f7 l.sb 0xfffffff7(r2),r3
> > 440: 8c 82 ff f7 l.lbz r4,0xfffffff7(r2) > 444: db e2 27
> ff l.sb 0xffffffff(r2),r4 > 448: 18 60 90 00 l.movhi
r3,0x9000
> > 44c: d7 e2 1f ec l.sw 0xffffffec(r2),r3 > 450: 84 82 ff ec
> l.lwz r4,0xffffffec(r2) > 454: a8 84 00 05 l.ori r4,r4,0x5
> > 458: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4 > 45c: 84 62 ff f0
> l.lwz r3,0xfffffff0(r2) > 460: 8c 63 00 00 l.lbz r3,0x0(r3)
> > 464: db e2 1f eb l.sb 0xffffffeb(r2),r3 > 468: 8c 82 ff eb
> l.lbz r4,0xffffffeb(r2) > 46c: db e2 27 fe l.sb
> 0xfffffffe(r2),r4 > 470: 8c 62 ff fe l.lbz r3,0xfffffffe(r2)
> > 474: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 > 478: 84 82 ff e4
> l.lwz r4,0xffffffe4(r2) > 47c: a4 84 00 20 l.andi
r4,r4,0x20
> > 480: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 > 484: 84 62 ff e0
> l.lwz r3,0xffffffe0(r2) > 488: bc 23 00 00 l.sfnei r3,0x0 >
> 48c: 10 00 00 04 l.bf 49c <_uart_putc+0x74> > 490: 15
00
> 00 00 l.nop 0x0 > 494: 03 ff ff ed l.j 448
> <_uart_putc+0x20> > 498: 15 00 00 00 l.nop 0x0 >
> 49c: 18 80 90 00 l.movhi r4,0x9000 > 4a0: d7 e2 27 dc
        l.sw
> 0xffffffdc(r2),r4 > 4a4: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
> > 4a8: db e2 1f db l.sb 0xffffffdb(r2),r3 > 4ac: 8c 62 ff db
> l.lbz r3,0xffffffdb(r2) > 4b0: 84 82 ff dc l.lwz
> r4,0xffffffdc(r2) > 4b4: d8 04 18 00 l.sb 0x0(r4),r3 >
> 4b8: 90 82 ff ff l.lbs r4,0xffffffff(r2) > 4bc: d7 e2 27 d4
> l.sw 0xffffffd4(r2),r4 > 4c0: 84 62 ff d4 l.lwz
> r3,0xffffffd4(r2) > 4c4: bc 23 00 0a l.sfnei r3,0xa >
> 4c8: 10 00 00 20 l.bf 548 <_uart_putc+0x120> > 4cc: 15
00
> 00 00 l.nop 0x0 > 4d0: 18 80 90 00 l.movhi r4,0x9000 >
> 4d4: d7 e2 27 cc l.sw 0xffffffcc(r2),r4 > 4d8: 84 62 ff cc
> l.lwz r3,0xffffffcc(r2) > 4dc: a8 63 00 05 l.ori r3,r3,0x5
> > 4e0: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3 > 4e4: 84 82 ff d0
> l.lwz r4,0xffffffd0(r2) > 4e8: 8c 84 00 00 l.lbz r4,0x0(r4)
> > 4ec: db e2 27 cb l.sb 0xffffffcb(r2),r4 > 4f0: 8c 62 ff cb
> l.lbz r3,0xffffffcb(r2) > 4f4: db e2 1f fe l.sb
> 0xfffffffe(r2),r3 > 4f8: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
> > 4fc: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4 > 500: 84 62 ff c4
> l.lwz r3,0xffffffc4(r2) > 504: a4 63 00 20 l.andi
r3,r3,0x20
> > 508: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3 > 50c: 84 82 ff c0
> l.lwz r4,0xffffffc0(r2) > 510: bc 24 00 00 l.sfnei r4,0x0 >
> 514: 10 00 00 04 l.bf 524 <_uart_putc+0xfc> > 518: 15
00
> 00 00 l.nop 0x0 > 51c: 03 ff ff ed l.j 4d0
> <_uart_putc+0xa8> > 520: 15 00 00 00 l.nop 0x0 >
> 524: 18 60 90 00 l.movhi r3,0x9000 > 528: d7 e2 1f bc
        l.sw
> 0xffffffbc(r2),r3 > 52c: 9c 80 00 0d l.addi r4,r0,0xd >
> 530: d7 e2 27 b8 l.sw 0xffffffb8(r2),r4 > 534: 84 62 ff b8
> l.lwz r3,0xffffffb8(r2) > 538: db e2 1f b7 l.sb
> 0xffffffb7(r2),r3 > 53c: 8c 62 ff b7 l.lbz r3,0xffffffb7(r2)
> > 540: 84 82 ff bc l.lwz r4,0xffffffbc(r2) > 544: d8 04 18
> 00 l.sb 0x0(r4),r3 > 548: 18 80 90 00 l.movhi
r4,0x9000 >
> 54c: d7 e2 27 ac l.sw 0xffffffac(r2),r4 > 550: 84 62 ff ac
> l.lwz r3,0xffffffac(r2) > 554: a8 63 00 05 l.ori r3,r3,0x5
> > 558: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 > 55c: 84 82 ff b0
> l.lwz r4,0xffffffb0(r2) > 560: 8c 84 00 00 l.lbz r4,0x0(r4)
> > 564: db e2 27 ab l.sb 0xffffffab(r2),r4 > 568: 8c 62 ff ab
> l.lbz r3,0xffffffab(r2) > 56c: db e2 1f fe l.sb
> 0xfffffffe(r2),r3 > 570: 8c 82 ff fe l.lbz r4,0xfffffffe(r2)
> > 574: d7 e2 27 a4 l.sw 0xffffffa4(r2),r4 > 578: 84 62 ff a4
> l.lwz r3,0xffffffa4(r2) > 57c: a4 63 00 60 l.andi
r3,r3,0x60
> > 580: d7 e2 1f a0 l.sw 0xffffffa0(r2),r3 > 584: 84 82 ff a0
> l.lwz r4,0xffffffa0(r2) > 588: bc 04 00 60 l.sfeqi r4,0x60
> > 58c: 10 00 00 04 l.bf 59c <_uart_putc+0x174> >
> 590: 15 00 00 00 l.nop 0x0 > 594: 03 ff ff ed l.j
548
> <_uart_putc+0x120> > 598: 15 00 00 00 l.nop 0x0 >
> 59c: 84 41 00 00 l.lwz r2,0x0(r1) > 5a0: 44 00 48 00
        l.jr r9
> > 5a4: 9c 21 00 64 l.addi r1,r1,0x64 > > 000005a8
> <_uart_getc>: > 5a8: 9c 21 ff d0 l.addi r1,r1,0xffffffd0
> > 5ac: d4 01 10 00 l.sw 0x0(r1),r2 > 5b0: 9c 41 00 30
> l.addi r2,r1,0x30 > 5b4: 18 60 90 00 l.movhi
r3,0x9000 >
> 5b8: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 > 5bc: 84 62 ff f0
> l.lwz r3,0xfffffff0(r2) > 5c0: a8 63 00 05 l.ori r3,r3,0x5
> > 5c4: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 > 5c8: 84 62 ff f4
> l.lwz r3,0xfffffff4(r2) > 5cc: 8c 63 00 00 l.lbz r3,0x0(r3)
> > 5d0: db e2 1f ef l.sb 0xffffffef(r2),r3 > 5d4: 8c 62 ff ef
> l.lbz r3,0xffffffef(r2) > 5d8: db e2 1f ff l.sb
> 0xffffffff(r2),r3 > 5dc: 8c 62 ff ff l.lbz r3,0xffffffff(r2)
> > 5e0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 > 5e4: 84 62 ff e8
> l.lwz r3,0xffffffe8(r2) > 5e8: ac 63 00 01 l.xori r3,r3,0x1
> > 5ec: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 > 5f0: 84 62 ff e4
> l.lwz r3,0xffffffe4(r2) > 5f4: a4 63 00 01 l.andi r3,r3,0x1
> > 5f8: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 > 5fc: 84 62 ff e0
> l.lwz r3,0xffffffe0(r2) > 600: bc 03 00 00 l.sfeqi r3,0x0 >
> 604: 10 00 00 04 l.bf 614 <_uart_getc+0x6c> > 608: 15
00
> 00 00 l.nop 0x0 > 60c: 03 ff ff ea l.j 5b4
> <_uart_getc+0xc> > 610: 15 00 00 00 l.nop 0x0 >
> 614: 18 60 90 00 l.movhi r3,0x9000 > 618: d7 e2 1f dc
        l.sw
> 0xffffffdc(r2),r3 > 61c: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
> > 620: 8c 63 00 00 l.lbz r3,0x0(r3) > 624: db e2 1f db
        l.sb
> 0xffffffdb(r2),r3 > 628: 8c 62 ff db l.lbz r3,0xffffffdb(r2)
> > 62c: db e2 1f fe l.sb 0xfffffffe(r2),r3 > 630: 90 62 ff fe
> l.lbs r3,0xfffffffe(r2) > 634: d7 e2 1f d4 l.sw
> 0xffffffd4(r2),r3 > 638: 84 62 ff d4 l.lwz r3,0xffffffd4(r2)
> > 63c: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 > 640: 85 62 ff f8
> l.lwz r11,0xfffffff8(r2) > 644: 84 41 00 00 l.lwz
r2,0x0(r1)
> > 648: 44 00 48 00 l.jr r9 > 64c: 9c 21 00 30 l.addi
> r1,r1,0x30 > > 00000650 <_main>: > 650: 9c 21 ff c4
> l.addi r1,r1,0xffffffc4 > 654: d4 01 10 04 l.sw 0x4(r1),r2
> > 658: 9c 41 00 3c l.addi r2,r1,0x3c > 65c: d4 01 48 00
> l.sw 0x0(r1),r9 > 660: 07 ff fe e8 l.jal 200
> <_uart_init> > 664: 15 00 00 00 l.nop 0x0 > 668: 18
60
> 00 00 l.movhi r3,0x0 > 66c: a8 63 07 44 l.ori
r3,r3,0x744 >
> 670: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 > 674: 84 62 ff f8
> l.lwz r3,0xfffffff8(r2) > 678: 84 63 00 00 l.lwz r3,0x0
(r3)
> > 67c: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 > 680: 84 62 ff f4
> l.lwz r3,0xfffffff4(r2) > 684: d7 e2 1f fc l.sw
> 0xfffffffc(r2),r3 > 688: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
> > 68c: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 > 690: 84 62 ff f0
> l.lwz r3,0xfffffff0(r2) > 694: 90 63 00 00 l.lbs r3,0x0(r3)
> > 698: d7 e2 1f ec l.sw 0xffffffec(r2),r3 > 69c: 84 62 ff ec
> l.lwz r3,0xffffffec(r2) > 6a0: bc 03 00 00 l.sfeqi r3,0x0 >
> 6a4: 10 00 00 13 l.bf 6f0 <_main+0xa0> > 6a8: 15
00 00 00
> l.nop 0x0 > 6ac: 84 62 ff fc l.lwz r3,0xfffffffc(r2) >
> 6b0: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 > 6b4: 84 62 ff e8
> l.lwz r3,0xffffffe8(r2) > 6b8: 90 63 00 00 l.lbs r3,0x0(r3)
> > 6bc: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 > 6c0: 84 62 ff e4
> l.lwz r3,0xffffffe4(r2) > 6c4: 07 ff ff 59 l.jal 428
> <_uart_putc> > 6c8: 15 00 00 00 l.nop 0x0 > 6cc: 84
62
> ff fc l.lwz r3,0xfffffffc(r2) > 6d0: d7 e2 1f e0 l.sw
> 0xffffffe0(r2),r3 > 6d4: 84 62 ff e0 l.lwz r3,0xffffffe0(r2)
> > 6d8: 9c 63 00 01 l.addi r3,r3,0x1 > 6dc: d7 e2 1f dc
        l.sw
> 0xffffffdc(r2),r3 > 6e0: 84 62 ff dc l.lwz r3,0xffffffdc(r2)
> > 6e4: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 > 6e8: 03 ff ff e8
> l.j 688 <_main+0x38> > 6ec: 15 00 00 00 l.nop 0x0 >
> 6f0: 07 ff ff ae l.jal 5a8 <_uart_getc> > 6f4: 15
00 00
> 00 l.nop 0x0 > 6f8: d7 e2 5f d8 l.sw 0xffffffd8(r2),r11 >
> 6fc: 84 62 ff d8 l.lwz r3,0xffffffd8(r2) > 700: 9c 63 00 01
> l.addi r3,r3,0x1 > 704: d7 e2 1f d4 l.sw 0xffffffd4
(r2),r3
> > 708: 84 62 ff d4 l.lwz r3,0xffffffd4(r2) > 70c: b8 63 00
> 18 l.slli r3,r3,0x18 > 710: d7 e2 1f cc l.sw 0xffffffcc
(r2),r3
> > 714: 84 62 ff cc l.lwz r3,0xffffffcc(r2) > 718: b8 63 00
> 98 l.srai r3,r3,0x18 > 71c: d7 e2 1f d0 l.sw 0xffffffd0
(r2),r3
> > 720: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) > 724: 07 ff ff
> 41 l.jal 428 <_uart_putc> > 728: 15 00 00 00 l.nop
0x0
> > 72c: 03 ff ff f1 l.j 6f0 <_main+0xa0> > 730: 15 00
> 00 00 l.nop 0x0 > 734: 85 21 00 00 l.lwz r9,0x0(r1) >
> 738: 84 41 00 04 l.lwz r2,0x4(r1) > 73c: 44 00 48 00
        l.jr r9
> > 740: 9c 21 00 3c l.addi r1,r1,0x3c > > > > -----
> Original Message ----- > From: Robert Cragie<rcc at j...>
> > To: > Date: Thu Nov 22 11:30:49 CET 2007 > Subject:
> [openrisc] how to run hello world in on-chip ram? > > >
> Can you post the disassembly of your hello.or32 file?: > >
> > > or32-uclinux-objdump -d hello.or32 > > > >
> That will give a clearer picture of where everything is. > >
> > > Robert > > > > Robert Cragie, Design Engineer
> > > >
>
_____________________________________________________________
 >
> __ > > Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
> > > http://www.jennic.com Tel: [phone] > >
> > _______________________________________________ >
> http://www.opencores.org/mailman/listinfo/openrisc 
>
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